Simulation Results: otbn

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.04 %
  • code
  • 82.27 %
  • assert
  • 90.86 %
  • func
  • 100.00 %
  • block
  • 97.81 %
  • line
  • 98.01 %
  • branch
  • 82.49 %
  • toggle
  • 82.39 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
97.55%
V2S
96.96%
V3
30.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 324.099us 1 1 100.00
single_binary 100 100 100.00
otbn_single 38.000s 1506.077us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 8.000s 52.228us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 8.000s 13.930us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 11.000s 318.034us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 8.000s 15.125us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 11.000s 273.113us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 8.000s 13.930us 5 5 100.00
otbn_csr_aliasing 8.000s 15.125us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 115.000s 5927.765us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 32.000s 323.375us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 74.000s 260.617us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 64.000s 192.376us 1 1 100.00
back_to_back 9 10 90.00
otbn_multi 130.000s 1380.659us 9 10 90.00
stress_all 9 10 90.00
otbn_stress_all 171.000s 1695.053us 9 10 90.00
lc_escalation 59 60 98.33
otbn_escalate 45.000s 119.340us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 7.000s 19.290us 5 5 100.00
sw_errs_fatal_chk 9 10 90.00
otbn_sw_errs_fatal_chk 24.000s 69.951us 9 10 90.00
alert_test 10 10 100.00
otbn_alert_test 10.000s 34.671us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 8.000s 20.018us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 11.000s 81.674us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 11.000s 81.674us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 8.000s 52.228us 1 1 100.00
otbn_csr_rw 8.000s 13.930us 5 5 100.00
otbn_csr_aliasing 8.000s 15.125us 1 1 100.00
otbn_same_csr_outstanding 5.000s 22.274us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 8.000s 52.228us 1 1 100.00
otbn_csr_rw 8.000s 13.930us 5 5 100.00
otbn_csr_aliasing 8.000s 15.125us 1 1 100.00
otbn_same_csr_outstanding 5.000s 22.274us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 13.000s 81.664us 10 10 100.00
otbn_dmem_err 20.000s 72.308us 15 15 100.00
internal_integrity 15 17 88.24
otbn_alu_bignum_mod_err 28.000s 286.112us 5 5 100.00
otbn_controller_ispr_rdata_err 13.000s 227.631us 5 5 100.00
otbn_mac_bignum_acc_err 17.000s 40.384us 3 5 60.00
otbn_urnd_err 9.000s 19.713us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 8.000s 19.361us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 11.000s 22.395us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 9.000s 33.040us 10 10 100.00
tl_intg_err 26 30 86.67
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
otbn_tl_intg_err 37.000s 208.301us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 53.000s 195.396us 4 5 80.00
prim_fsm_check 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
prim_count_check 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 324.099us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 20.000s 72.308us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 13.000s 81.664us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 37.000s 208.301us 25 25 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 45.000s 119.340us 59 60 98.33
sec_cm_controller_fsm_local_esc 36 40 90.00
otbn_imem_err 13.000s 81.664us 10 10 100.00
otbn_dmem_err 20.000s 72.308us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 19.290us 5 5 100.00
otbn_illegal_mem_acc 8.000s 19.361us 5 5 100.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_controller_fsm_sparse 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 38.000s 1506.077us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 36 40 90.00
otbn_imem_err 13.000s 81.664us 10 10 100.00
otbn_dmem_err 20.000s 72.308us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 19.290us 5 5 100.00
otbn_illegal_mem_acc 8.000s 19.361us 5 5 100.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_scramble_ctrl_fsm_sparse 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 45.000s 119.340us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 36 40 90.00
otbn_imem_err 13.000s 81.664us 10 10 100.00
otbn_dmem_err 20.000s 72.308us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 19.290us 5 5 100.00
otbn_illegal_mem_acc 8.000s 19.361us 5 5 100.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_start_stop_ctrl_fsm_sparse 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 38.000s 1506.077us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 16.000s 53.718us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 24.709us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 99.000s 1833.391us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 99.000s 1833.391us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 13.000s 87.824us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_stack_wr_ptr_ctr_redun 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_rf_bignum_data_reg_sw_integrity 10 10 100.00
otbn_rf_bignum_intg_err 24.000s 117.863us 10 10 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_loop_stack_ctr_redun 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 22.000s 44.291us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 22.000s 44.291us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 22.000s 41.193us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 38.000s 1506.077us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 38.000s 1506.077us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 38.000s 1506.077us 100 100 100.00
sec_cm_write_mem_integrity 9 10 90.00
otbn_multi 130.000s 1380.659us 9 10 90.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 38.000s 1506.077us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 38.000s 1506.077us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 25.000s 260.860us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 38.000s 1506.077us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 1 5 20.00
otbn_sec_cm 608.000s 13686.270us 1 5 20.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 428.000s 15415.634us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 9.000s 154.137us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
otbn_stress_all_with_rand_reset 10293672483566605792329614954889146386434137453985802127611762041004075800035 171
UVM_INFO @ 131316254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 106689362950297555725652825062553214996351252970168378371725838729775864515137 287
UVM_INFO @ 1303127432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 45478374286150222235872100615033990213852342798616893729382020576881396139765 254
UVM_INFO @ 1187388733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 19163731036026881089631561779563668781839688523425306833203269463716776094750 318
UVM_INFO @ 2108530897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 115342886079712960814324900884372123440536856901545175001084582685632073466232 394
UVM_INFO @ 1670564044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 4 test runs
otbn_sec_cm 84188875847637471160128915904042773494347921690032036544881955995395818886625 93
UVM_ERROR @ 22923189 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 22923189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 71387243158933498802742759900332521129218898193095871302557151401293891795435 108
UVM_ERROR @ 35782260 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 35782260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 69760107704591552869156872802879615312750806515946169279095697701430828857554 107
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 361681878 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 361681878 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 361681878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sec_cm 114706249988926093991266444260537461701461527932899501995050641096738530274878 117
UVM_ERROR @ 697184790 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 697184790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 3 test runs
otbn_mac_bignum_acc_err 107102233034986866075509288276362366751379027432577852698630332465943183588869 125
UVM_INFO @ 289065768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_mac_bignum_acc_err 106449468513207510972617310863991803785933288400969643973293738874873270840904 123
UVM_INFO @ 89841247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_sw_errs_fatal_chk 103031357082684915189718634709745163727260431610255530416167101962892058439842 106
UVM_INFO @ 38176494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 2 test runs
otbn_multi 69430766467675891588932371971362076057516551159806781045334165169385211594811 193
UVM_INFO @ 412880253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 86634725648575485491848093505318713794848541330605705659770286959482657133466 86
UVM_INFO @ 5607884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_stack_addr_integ_chk 83707713812183382035489858913264859409624527715417959940241368575790555467962 118
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 4924914 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 4924914 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 4924914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 76849135383854891460168230496263508021749743400829206742278320250705761204093 113
UVM_ERROR @ 60862129 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 60862129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_stress_all 15467323437967199826973310570256408208496021264396405581878337849744247317953 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 71437691387368487556762961323654614475340217172222844168065793254466095448957 615
UVM_INFO @ 2735527189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 76455951333117642316286125726263931247417498085070052072839475929088274890146 346
UVM_INFO @ 1375877293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---