Simulation Results: rom_ctrl/32kb

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.94 %
  • code
  • 94.00 %
  • assert
  • 97.53 %
  • func
  • 99.29 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
93.22%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.000s 187.851us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 5.000s 709.723us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 5.000s 211.729us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 1407.762us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.000s 540.086us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 822.211us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 5.000s 211.729us 5 5 100.00
rom_ctrl_csr_aliasing 4.000s 540.086us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 475.129us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 4.000s 536.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.000s 440.569us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 23.000s 8055.751us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 6.000s 305.679us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.000s 165.947us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 851.493us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 9.000s 851.493us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.000s 709.723us 1 1 100.00
rom_ctrl_csr_rw 5.000s 211.729us 5 5 100.00
rom_ctrl_csr_aliasing 4.000s 540.086us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 173.007us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 5.000s 709.723us 1 1 100.00
rom_ctrl_csr_rw 5.000s 211.729us 5 5 100.00
rom_ctrl_csr_aliasing 4.000s 540.086us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 173.007us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.000s 3106.701us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 145.000s 1823.248us 5 5 100.00
rom_ctrl_tl_intg_err 39.000s 3840.695us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 145.000s 1823.248us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 145.000s 1823.248us 5 5 100.00
sec_cm_checker_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
sec_cm_checker_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
sec_cm_checker_fsm_local_esc 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
sec_cm_compare_ctrl_flow_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
sec_cm_compare_ctr_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 145.000s 1823.248us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 145.000s 1823.248us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.000s 187.851us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.000s 187.851us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.000s 187.851us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 39.000s 3840.695us 25 25 100.00
sec_cm_bus_local_esc 18 22 81.82
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
rom_ctrl_kmac_err_chk 6.000s 305.679us 2 2 100.00
sec_cm_mux_mubi 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
sec_cm_mux_consistency 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
sec_cm_ctrl_redun 16 20 80.00
rom_ctrl_corrupt_sig_fatal_chk 85.000s 3348.787us 16 20 80.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 24.000s 3106.701us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 145.000s 1823.248us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
rom_ctrl_stress_all_with_rand_reset 119.000s 10139.635us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 4 test runs
rom_ctrl_corrupt_sig_fatal_chk 80458764825017734078145106367739741973041936995218327252985946990046357021873 99
UVM_INFO @ 3850660248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 72780245412179658462552223820210096497951853578338086591700024975241251669378 100
UVM_INFO @ 1632401411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 76400448516821261319482399229225149938613043291021843653898680278341948860771 93
UVM_INFO @ 4228225244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 62317110610248142198155737911696311219781791301322275556140386115936123576019 96
UVM_INFO @ 781424362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 94271496551199883958993564783638538131029268040903776414377146787708150788525 88
UVM_INFO @ 129813201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 90416370856744504664992933630657571284604100906275555658373029145334151824776 88
UVM_INFO @ 440569457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 2 test runs
rom_ctrl_stress_all_with_rand_reset 59940101989071651304024431078271961488894084861563633429884944658575137342819 92
UVM_INFO @ 2916810689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 60132594517456493361027076441181492867675768596350790215600363382320667960173 91
UVM_INFO @ 279235115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---