Simulation Results: rom_ctrl/64kb

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.91 %
  • code
  • 94.01 %
  • assert
  • 97.67 %
  • func
  • 99.06 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 9.000s 841.923us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.000s 546.890us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 8.000s 291.438us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.000s 206.975us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.000s 1030.313us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 10.000s 2134.630us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 8.000s 291.438us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 1030.313us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.000s 1682.406us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.000s 385.393us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 6.000s 259.459us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 31.000s 1111.145us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 16.000s 21911.967us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 7.000s 205.782us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 10.000s 730.355us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 10.000s 730.355us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.000s 546.890us 1 1 100.00
rom_ctrl_csr_rw 8.000s 291.438us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 1030.313us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 1034.558us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.000s 546.890us 1 1 100.00
rom_ctrl_csr_rw 8.000s 291.438us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 1030.313us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.000s 1034.558us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.000s 3069.793us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 258.000s 1310.139us 5 5 100.00
rom_ctrl_tl_intg_err 73.000s 1196.531us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 258.000s 1310.139us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 258.000s 1310.139us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 258.000s 1310.139us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 258.000s 1310.139us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 9.000s 841.923us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 9.000s 841.923us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 9.000s 841.923us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 73.000s 1196.531us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
rom_ctrl_kmac_err_chk 16.000s 21911.967us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 134.000s 4452.656us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.000s 3069.793us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 258.000s 1310.139us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
rom_ctrl_stress_all_with_rand_reset 131.000s 10034.369us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 33395712186201020210387508019574160110414900389077359770999115709528504043544 88
UVM_INFO @ 259459152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 82346978403736209563512879082874866332173933451897287732081994659728193362113 88
UVM_INFO @ 690404343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 2 test runs
rom_ctrl_stress_all_with_rand_reset 61113333934819245922457992330601239738686688117947737530024926043246107281595 94
UVM_INFO @ 2498203340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 112311095176698391795220995299478087369487279202402150472994152690884069466233 90
UVM_INFO @ 239838973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---