Simulation Results

Simulation Results: rv_dm/use_dmi_interface

26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.83 %

code
83.29 %

assert
96.74 %

func
98.45 %

block
93.79 %

line
94.28 %

branch
83.18 %

toggle
75.34 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		42.22%
V2S		98.00%
V3		5.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	44.000s	1546.103us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	41.000s	576.834us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	52.000s	651.551us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	59.000s	22943.657us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	50.000s	1443.864us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	53.000s	2659.595us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	50.000s	3564.422us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	75.000s	52987.350us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	442.000s	268061.715us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	38.000s	620.771us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	39.000s	349.979us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	40.000s	235.923us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	45.000s	215.412us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	39.000s	128.458us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	38.000s	1005.772us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	41.000s	348.129us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	50.000s	1461.836us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	38.000s	620.771us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	41.000s	129.185us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	41.000s	190.325us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	40.000s	235.923us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	50.000s	73.103us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	40.000s	99.312us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	46.000s	265.492us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	77.000s	8302.034us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	48.000s	680.126us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	46.000s	310.592us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	48.000s	680.126us	1	1	100.00
	rv_dm_csr_rw	46.000s	265.492us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	39.000s	50.197us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	49.000s	74.457us	1	1	100.00

76/180 passed

42.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	44.000s	1546.103us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	45.000s	357.661us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	51.000s	665.249us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	38.000s	83.621us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	44.000s	1391.426us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	68.000s	12706.289us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	51.000s	152.035us	0	20	0.00
bad_sba				1	20	5.00
	rv_dm_bad_sba_tl_access	61.000s	6640.792us	1	20	5.00
sba_autoincrement				2	20	10.00
	rv_dm_autoincr_sba_tl_access	111.000s	47718.910us	2	20	10.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	40.000s	296.311us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	48.000s	2427.899us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	34.000s	219.932us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	46.000s	54.160us	0	5	0.00
tap_ctrl_transitions				10	11	90.91
	rv_dm_tap_fsm	54.000s	7723.501us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	96.000s	4508.394us	9	10	90.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	43.000s	110.804us	1	1	100.00
stress_all				1	20	5.00
	rv_dm_stress_all	10800.000s	0.000us	1	20	5.00
alert_test				10	10	100.00
	rv_dm_alert_test	45.000s	141.347us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	50.000s	167.167us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	50.000s	167.167us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	48.000s	680.126us	1	1	100.00
	rv_dm_csr_hw_reset	40.000s	99.312us	1	1	100.00
	rv_dm_csr_rw	46.000s	265.492us	5	5	100.00
	rv_dm_same_csr_outstanding	48.000s	2266.155us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	48.000s	680.126us	1	1	100.00
	rv_dm_csr_hw_reset	40.000s	99.312us	1	1	100.00
	rv_dm_csr_rw	46.000s	265.492us	5	5	100.00
	rv_dm_same_csr_outstanding	48.000s	2266.155us	5	5	100.00

V2S

49/50 passed

98.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	44.000s	885.024us	5	5	100.00
	rv_dm_tl_intg_err	62.000s	6870.745us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	62.000s	6870.745us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	48.000s	2427.899us	2	2	100.00
	rv_dm_debug_disabled	39.000s	79.625us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	48.000s	2427.899us	2	2	100.00
	rv_dm_debug_disabled	39.000s	79.625us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	44.000s	1546.103us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				9	10	90.00
	rv_dm_buffered_enable	48.000s	596.869us	9	10	90.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	46.000s	81.438us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	46.000s	81.438us	4	4	100.00
sec_cm_exec_ctrl_mubi				9	10	90.00
	rv_dm_buffered_enable	48.000s	596.869us	9	10	90.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	20	5.00
	rv_dm_stress_all_with_rand_reset	70.000s	14660.803us	1	20	5.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	167.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				40 test runs
	rv_dm_sba_tl_access	69537305773629726065151050058866473697758691119334597079261256364177425963587	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23863
	rv_dm_bad_sba_tl_access	76470298131593101338453388831125599810778250300767565615951725067185273283228	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23782
	rv_dm_autoincr_sba_tl_access	67290902349346831908473305618110615272583096630221931781276863196508953270079	138	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23961
	rv_dm_sba_tl_access	15091585688422956140422036967068507830896082045244767035743699043155056634521	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23865
	rv_dm_autoincr_sba_tl_access	94749528559620418844198337181637796215521395714522825902742700191616392210528	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23726
	rv_dm_sba_tl_access	79240156921855021839274440562882658448151420952788587307059546214089735626880	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23878
	rv_dm_bad_sba_tl_access	4097070606199440399998906227176398757732171250364303646396128827730361928728	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_sba_tl_access	109875665517074504068516233951912275987894970011013064213296583531376246835948	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23812
	rv_dm_autoincr_sba_tl_access	113889649064631704722325078117169319835723820215161850097921659188978210776929	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23821
	rv_dm_sba_tl_access	46014385193342667883189446170909151176477520085675637599023683613245018405768	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23856
	rv_dm_sba_tl_access	16410245778020758808605454433102285908672745153034119694857865949249879482753	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_sba_tl_access	82352903735335382511726179579124991097454938050883297940712872954765159714802	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23861
	rv_dm_sba_tl_access	37855725998914861748389396644299758186515889398500405662901128010341425020327	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23799
	rv_dm_autoincr_sba_tl_access	73482921569802173096852673936088901033894279897520409041467254813083001675327	138	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23898
	rv_dm_sba_tl_access	26705680058268579904922250911092463696719801732667529860903784267445253600016	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_bad_sba_tl_access	41288718009503098381453766753813801255558267290036553514066865770424352977351	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23776
	rv_dm_autoincr_sba_tl_access	85312549238318504292361282910841461132546414634274856776883596882093625487069	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
	rv_dm_sba_tl_access	61586023977478469519926674687364044488491919698607463922693842254374924384843	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23876
	rv_dm_bad_sba_tl_access	25988967519349163326470528736824510696662785043161644941221885261874548207702	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23941
	rv_dm_sba_tl_access	42185002281168194152818970481428786802031337928597410353504454086888763407028	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23858
	rv_dm_bad_sba_tl_access	102673338631264074309147381516590836920925687760201642845216969493814817373896	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23889
	rv_dm_autoincr_sba_tl_access	105815885641679602308399408882308205418539996372086689364406782813432451427013	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23914
	rv_dm_sba_tl_access	51051534361246973183294138139100110845432477552067839678733087447318662287496	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23785
	rv_dm_autoincr_sba_tl_access	90220889277842611875988950289501467421835194773649180467217440694797213669528	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10111
	rv_dm_sba_tl_access	71580914605803124213146661170094794866150941863349755366173888880959784838730	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23783
	rv_dm_bad_sba_tl_access	106160588300902633774025582967695573798914413995058621178369285623408315806893	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23889
	rv_dm_autoincr_sba_tl_access	34626126695024727699023864033040152616251367815934443683864635859161118861186	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_sba_tl_access	108248158398607757146285750689130249065986295959218950908895919430733663707065	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23816
	rv_dm_autoincr_sba_tl_access	67913954500355876625470201967409748497343650026922113815329178036231514682309	129	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23813
	rv_dm_sba_tl_access	28050338313342672202059425788158270479137277814110606715264122000331922963671	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23814
	rv_dm_bad_sba_tl_access	23510204707259874479918104775426858449430800692505370538608199868562558176435	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_sba_tl_access	102245255537329647070280579223254767553507349103682303226942966645982990732868	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23813
	rv_dm_sba_tl_access	76957324593683118378983021312269442121905558382872393207623643219611491035771	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23806
	rv_dm_autoincr_sba_tl_access	113409397363756477517771523422200699955740870224228830260317829994595172800428	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_sba_tl_access	110915933062263917721880057557428056995605976376769460022630943033510414411636	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23833
	rv_dm_bad_sba_tl_access	61266418376485572706784187006610371456866885723059363641977160991655000330350	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24010
	rv_dm_sba_tl_access	7783765049338310355744062523666528492555626029817329086592557008914530676943	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23805
	rv_dm_bad_sba_tl_access	100099121199295949117845250229916652225766388924070043763763658530828240784118	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23859
	rv_dm_sba_tl_access	1999460960931398060718515250725708145702266094779419781854118488053009707176	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23891
	rv_dm_bad_sba_tl_access	20327399466031985188462819071555437348444211811896574838137769416402786678375	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10069
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				37 test runs
	rv_dm_delayed_resp_sba_tl_access	104129862863588521851288633232191357018469948355704418798855605719037112281219	107	UVM_INFO @ 71455789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	55211300247533121830799585270129916518540871159920454653979585354538310980165	107	UVM_INFO @ 203238843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	102850188014581028599233608725467783664307442441873092732064105217635569333891	107	UVM_INFO @ 145592156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	16604288227305088083072280015471169967162927608043479364274820362400221542003	107	UVM_INFO @ 152034612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	73922195773741985159224905154069010669176762376731299561353365493375780975230	107	UVM_INFO @ 79338647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	30375430884288736707826700807750727070098932707455841948071322957075659335839	107	UVM_INFO @ 77243234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	95562542402645668614204820575905723997247508378641262005587149300225091023	107	UVM_INFO @ 72554534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	93298298095431989979197076857488578642295748223375637555596285770043978052675	107	UVM_INFO @ 161368809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	20355463317466542588224302260073683297148297656978112487079682502684249937111	107	UVM_INFO @ 428448238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	5544372063866374378790315543329423708624701850074615004984633761608372665922	107	UVM_INFO @ 85592115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	79364790692977671356106169678433420939725896755069845465562552643216546368761	107	UVM_INFO @ 156171349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	26362197524961090215395195531087872702265060579399290203203448290209337243446	107	UVM_INFO @ 462256606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	98992104951471141498852110438955410151744083137463000174805410019801078493687	107	UVM_INFO @ 64283558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	12515112468587930247898393353683568861010478399921421863845377605563816987631	107	UVM_INFO @ 60690698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	76062577936155884411475211224229573315319434005304753169292564880069855518010	116	UVM_INFO @ 16650330169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	74201547337598851224123904786139484421118425482604914492315902742963558235649	107	UVM_INFO @ 71730035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	71894454456621464980365571486002470795847411967845862841344599645947470390837	107	UVM_INFO @ 262452023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	68263580241233914011768244998298009198867002469921402063479009603921038503992	107	UVM_INFO @ 83641075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	44489530998649068827156390468000148578119727339375773546300863280681905207952	107	UVM_INFO @ 40278997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	99592753402752917358728615744122183541617165053475996562175135447814760612181	107	UVM_INFO @ 66525992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	113551186726719337043240035649796586123413351178441177336633158293796678129738	107	UVM_INFO @ 117035148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	30455527803579097611997591693617835088506582757521608359580989409684477949321	107	UVM_INFO @ 53450414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	39045722781842865624813673001851258862288737247404194446422961107221812214911	107	UVM_INFO @ 321380016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	77572518476736347780099397452873440912936744510041250758711375520769159361058	107	UVM_INFO @ 141608075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	98438962661283411948235071718039652388066096079238403430789445356113677482358	107	UVM_INFO @ 108391514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	107667472203618410028564307526878675833656246444848608571301645363754543903343	107	UVM_INFO @ 278740628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	51737903338902598275990306492384072715623442857271947385328132227692698322392	107	UVM_INFO @ 16538543615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	7949342027220076594936360887287423787413635642914173616256174856392364893679	107	UVM_INFO @ 149225876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	28088803185518789979708386038212552603510148991120108851172418400000578622849	107	UVM_INFO @ 64147661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	94538293902526545944063335552451030021547457876674675613416206408406129000343	107	UVM_INFO @ 76906272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	14628788712980169149705366453247221230862401883156903121882588941833298691825	107	UVM_INFO @ 64053250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	51579883846761471220787419415744276974807269026510171249581463790145081781075	107	UVM_INFO @ 74598838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	115682653364050685192298987041442919543460141676170465664234958072712131996625	107	UVM_INFO @ 61792860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	48734873344969881145698182751571372728539127548094020083452214128310146808529	107	UVM_INFO @ 86788861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	89752321469044781706150050569793933253027877001446382855921275004129638098713	107	UVM_INFO @ 524301465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	57982449340278192447317221442179104549559104281418428966688839895134538369474	107	UVM_INFO @ 175515016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	109024565630156487690706631099386416278365386186886402455010973608844069385154	107	UVM_INFO @ 42009476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				18 test runs
	rv_dm_hart_unavail	62242871421206134780945212322340167255552658956439381190986798110735347003634	87	UVM_INFO @ 107864808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	83639954214751195514833981638670171998475713496324923308045264215844920489833	91	UVM_INFO @ 283233161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	23998946024657791747845908133655953506022655720693245796208466896064533012552	87	UVM_INFO @ 54160292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	47852707323786616443859223750515363274387177975527480859356869529645173350710	106	UVM_INFO @ 604491278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	109604287609441983056696998299763076168775386862802575496930298794869361316536	87	UVM_INFO @ 224618866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	77918719403599067048023632053665103963584808219183145802153336330941148667420	87	UVM_INFO @ 158508101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	38827470711383701863541425815705866600897881695153092043331229139903592818132	91	UVM_INFO @ 151696264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	49305311157264839390597794278262343019994250531249693227036920632333291142181	87	UVM_INFO @ 117808643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	100130322066648704085713535982827455858786103353676281756136119890415013466717	110	UVM_INFO @ 838392738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	20464254202488317200437055825626386652006813502508076915247833566024142128716	110	UVM_INFO @ 1241926153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	21901775127905929723064033833545003174483712145340170407357697267786971156004	89	UVM_INFO @ 329722055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	83563826491330762204237016095673793192294384854036637043173385449877982039465	96	UVM_INFO @ 2044822246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	51443933880158059885712471577425701248259987154805639203783525178931603981864	92	UVM_INFO @ 265246543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	93685395603497709078434966097702643679263826850313046916157598657169966875610	117	UVM_INFO @ 2818097988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	20746682136029121914841193634005042733685147919407887333195519596738603629137	92	UVM_INFO @ 1181979908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	44239869891556562376644022120438351306456587645880540231530592881683511394159	91	UVM_INFO @ 1264839905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	65846888736580252207815016363354561763162816652008675641584142522306597691652	92	UVM_INFO @ 3854534190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	5778382790050780261764217361659016106597005759451433568984799368364270354280	98	UVM_INFO @ 1840672161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				11 test runs
	rv_dm_mem_tl_access_resuming	113288643278187200941025164262148592023843708706799628077455002381356363810401	87	UVM_INFO @ 75361401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	78923883406597999381627157515590308615284524359854469833549727389346608128161	88	UVM_INFO @ 124823473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	16415712693090238908346835179301615036917098046625860498601864784667162653259	87	UVM_INFO @ 215412262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	35271002974916138507309208268846061687430329899547318123285141916753278517033	91	UVM_INFO @ 956390290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	67969359263715970336096275069822222149950256535752013346912080285405034767682	89	UVM_INFO @ 4499780051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	43048246627279614717621069301864674063538230580297157768856499012326631307306	93	UVM_INFO @ 331693222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	89289855440526871083498293753172307401746919971040211213112642033814691293046	91	UVM_INFO @ 1090608703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	8795891814400785232216714764614889443866330002535946485294771010906930610994	124	UVM_INFO @ 2597213052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	93158596046238315625068332207459043257544335891690654160402055424358642705405	89	UVM_INFO @ 480384755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	107549583262886375433128446210727898139796717189696854821054964498021889357658	96	UVM_INFO @ 1352883451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	10906633973139702756545074379976588639881393742696099433045377451686924519339	108	UVM_INFO @ 779572596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				7 test runs
	rv_dm_jtag_dmi_debug_disabled	21665264756701347408247455605933488830996788658134553156838105726607078065126	87	UVM_INFO @ 76678834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	62057871275286043567629596351692208946691327668480662525515730969877121657117	87	UVM_INFO @ 296310714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	7547882032265413701279743808358310847066737525216471999506720975417716896014	89	UVM_INFO @ 425968941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72408501558639965288901825732483269853519519717512023698064011461422018410334	88	UVM_INFO @ 272761114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	67134022828344179629639983653295242703722706110691730220987546645098400402152	100	UVM_INFO @ 1814049852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	81672344277142888165067103808131176341584843152306219469464530479436793938041	91	UVM_INFO @ 1363643809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	12108402929524946995995778592350556607794367907047780209933514046022334943076	88	UVM_INFO @ 142083614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				6 test runs
	rv_dm_tap_fsm_rand_reset	6041971634023511593836080560648910400071724324860886527912929510371435075979	153	UVM_INFO @ 6684083166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	28674449425877236369535656731087503830858239373682268506169971231639798139973	97	UVM_INFO @ 1560808084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	93721914300624502339461069196963667428514058232398788912931927445669695282201	105	UVM_INFO @ 1275815062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	47092685023831338385789605431550075780788960956469923509168291696255642434660	99	UVM_INFO @ 2271983229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	54371047239757412370505065011975441234134960178730767039443587358286783105153	106	UVM_INFO @ 1105318157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	83913983876034623377476039342870776880576629195472128283285237705021844116277	149	UVM_INFO @ 14660802571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				4 test runs
	rv_dm_scanmode	98537085462941638944949412568801426277769075820185024256419284160957044966070	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	46694715925392175410075449956776632550072341920469202177509488816303788714083	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	77964218563613230630803718870006914418742158534637048310664869446430792216042	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	1540155126743258914805634807009003040787758784199938989184020980896106666450	92	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				3 test runs
	rv_dm_stress_all	74634093860366035565997369705771905845109916256252098321393115722066696966521	None
	rv_dm_stress_all	13983286161588572917672313583139266093845679548606720351123969581987136071933	None
	rv_dm_stress_all	80631748541328686270489317249062258692275521684835486316508737714598048364476	None
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				1 test run
	rv_dm_buffered_enable	61894295225204397746468905315002730695116138316578662160544156545562746830450	89	UVM_INFO @ 596868554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---