Simulation Results: rv_timer

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 90.45 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
85.04%
V2S
100.00%
V3
55.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 530.900us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 2.000s 14.346us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 1.000s 44.785us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 5.000s 970.823us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 59.422us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 61.414us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 1.000s 44.785us 5 5 100.00
rv_timer_csr_aliasing 1.000s 59.422us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 20 5.00
rv_timer_random_reset 10.000s 97004.177us 1 20 5.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 1421.082us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 594.000s 1781295.898us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 594.000s 1781295.898us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 13.000s 6299.452us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 1.000s 38.903us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 1.000s 20.627us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 569.106us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 569.106us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 2.000s 14.346us 1 1 100.00
rv_timer_csr_rw 1.000s 44.785us 5 5 100.00
rv_timer_csr_aliasing 1.000s 59.422us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 20.987us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 2.000s 14.346us 1 1 100.00
rv_timer_csr_rw 1.000s 44.785us 5 5 100.00
rv_timer_csr_aliasing 1.000s 59.422us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 20.987us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.000s 349.270us 5 5 100.00
rv_timer_tl_intg_err 2.000s 132.166us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 132.166us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 5 10 50.00
rv_timer_min 2.000s 120.664us 5 10 50.00
max_value 0 10 0.00
rv_timer_max 1.000s 48.422us 0 10 0.00
stress_all_with_rand_reset 17 20 85.00
rv_timer_stress_all_with_rand_reset 54.000s 29124.110us 17 20 85.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 24 test runs
rv_timer_random_reset 48071804607487545134931225639634384407807752317612616578953090486888805966674 85
UVM_INFO @ 179003436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 33972713347910812848322971073446686040054895825714583223182290543666003299192 84
UVM_INFO @ 758650722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 1793533973930004138331414051236259092035588778580324528166886192419912229427 85
UVM_INFO @ 127102197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 10185583054095640934355590923218667647757746480034562639392914255894966043635 87
UVM_INFO @ 453440043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 31827138769276772269487574235271208050865212672584778383659045683626333059685 86
UVM_INFO @ 120664220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 21956934033761525299546598902339837412768476672797797335258214654057488958321 84
UVM_INFO @ 97695375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 56164453186616656903881717134832773808120083422063528790080258814072376786623 84
UVM_INFO @ 160698976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 54709987930080833900570471877758502652714870346580726063841901337808955062097 84
UVM_INFO @ 62548983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 44434478424249503842125876016769744803736091929366341172672916254123292997051 84
UVM_INFO @ 148556796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 53601428199064368609000414130677568516837937730758582010259469078517296640538 84
UVM_INFO @ 75595474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 53668343158370298908401782832793284101675933181249488966725301408106131039587 84
UVM_INFO @ 97004176814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 112828940564537902602186346169968720179729532609090730907836334024379026461705 86
UVM_INFO @ 142078891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 42931088479979363715836096186862378507086211382330085395574903620397403248254 84
UVM_INFO @ 148915790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 3880150265169091261976976260918851234202473235167465845226251657049255910807 85
UVM_INFO @ 295014814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 58725679356952998531192615183257682868700341282955342938899096016576522656559 85
UVM_INFO @ 105365933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 91795490159789639331579141885427259271954587970385591970650971145588426340046 85
UVM_INFO @ 1977937652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 110713156731770027469386258606481547077857431046313687219387362245199443950578 84
UVM_INFO @ 293298252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 95898876070412287685941202924158651448627798450566448853105456282270199868044 84
UVM_INFO @ 3710210795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 89957771893046729266623868571343877259991075907178465742897420410657836170323 84
UVM_INFO @ 577162238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 2452738223397018989100665909226343891346659267941004958839389124261101945489 84
UVM_INFO @ 160441800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 16317867437310045146737143882867565720395484605547908112071452399092773217728 84
UVM_INFO @ 532523732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 74000170269580627781033598122347827737238460310180645186273600798355339229138 84
UVM_INFO @ 871289224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 7978483649878748947460733031532859232118833133898517728143559972498680332615 84
UVM_INFO @ 95636975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 73263239760674772579771149704294325759493242305741215275250102598903051355496 84
UVM_INFO @ 726887059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 13149186491976412932796724854175013452467659204812022627901200842023577884298 84
UVM_INFO @ 48422233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 45658935858644023272167496317908503435176135653172049290311458879014211366512 84
UVM_INFO @ 48504904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 17413140086382489782812782917208354533777217293971477785621628858836243495813 84
UVM_INFO @ 47840085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 64154894587828747220413196658918756160220424964194482474956735424613865347341 84
UVM_INFO @ 901920401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 19673138160711507679033938731752802166227083615430084695113738721271760096360 84
UVM_INFO @ 50641894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 2290218709756983700835508569078061369399324944927155921789640821814270532784 84
UVM_INFO @ 47190712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 61971072212719975398333855436982638996760309977390727319269555133732450430367 84
UVM_INFO @ 159378471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 59701285824621132246552556503954036651451436171526514238771451589510417287174 84
UVM_INFO @ 180482562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 69898234420789367599884519166525188374296887630429051894474106774884933706153 84
UVM_INFO @ 206148815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
rv_timer_stress_all_with_rand_reset 41768638469595161203363685414596558928616491447381960836943833141293217690458 376
UVM_INFO @ 3885529683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 49482167081308885328370095843675471689745851222192495420629783357073874578349 463
UVM_INFO @ 4517926659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 62674488218949697122437380668549062410743118682573542410672253004759882317866 219
UVM_INFO @ 8951332061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 51646354035378181143289501935951395020523715898487943912967362479841674121730 84
UVM_INFO @ 44550910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---