Simulation Results: spi_host

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.57 %
  • code
  • 91.30 %
  • assert
  • 95.65 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 74.000s 2871.214us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 32.102us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 20.223us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 645.688us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 52.862us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 62.192us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 20.223us 5 5 100.00
spi_host_csr_aliasing 2.000s 52.862us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 30.198us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 54.874us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 41.266us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 4.000s 93.042us 10 10 100.00
spi_host_error_cmd 2.000s 18.629us 10 10 100.00
spi_host_event 61.000s 6159.143us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 801.902us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 801.902us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 801.902us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 479.000s 34102.602us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 16.000s 589.864us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 84.152us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 801.902us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 801.902us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 74.000s 2871.214us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 74.000s 2871.214us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 101.000s 14611.080us 10 10 100.00
spien 9 10 90.00
spi_host_spien 37.000s 10128.588us 9 10 90.00
stall 10 10 100.00
spi_host_status_stall 160.000s 6275.821us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 12.000s 8225.606us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 4.000s 93.042us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 29.716us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 18.370us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 141.800us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 141.800us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 32.102us 1 1 100.00
spi_host_csr_rw 2.000s 20.223us 5 5 100.00
spi_host_csr_aliasing 2.000s 52.862us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 81.113us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 32.102us 1 1 100.00
spi_host_csr_rw 2.000s 20.223us 5 5 100.00
spi_host_csr_aliasing 2.000s 52.862us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 81.113us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 215.403us 25 25 100.00
spi_host_sec_cm 2.000s 72.135us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 215.403us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_spien 56973005822379907013651842671540220591521184942930443974128630748038449432742 343
UVM_INFO @ 10128588118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---