Simulation Results: sram_ctrl/ret

 
26/06/2026 15:00:32 DVSim: v1.49.0 sha: 9b639d2 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.39 %
  • code
  • 82.50 %
  • assert
  • 98.08 %
  • func
  • 96.60 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 2.000s 69.914us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 17.484us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 14.077us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 35.794us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 50.013us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 74.504us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 14.077us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 50.013us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 12.000s 6365.745us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 7.000s 172.133us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 16.000s 1463.886us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 217.000s 3755.551us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 10.000s 1497.840us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 21.000s 2571.260us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 10.000s 3147.597us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 14.000s 3564.393us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 2.000s 64.115us 8 8 100.00
sram_ctrl_partial_access_b2b 344.000s 79913.354us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 76.107us 0 8 0.00
sram_ctrl_throughput_w_partial_write 2.000s 69.885us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 127.750us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 13.000s 832.250us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 27.935us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 75.000s 61326.858us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 34.509us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 134.158us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 7.000s 134.158us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 17.484us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.077us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 50.013us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 58.892us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 17.484us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.077us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 50.013us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 58.892us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1529.016us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 4.000s 636.810us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 794.824us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 4.000s 636.810us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 794.824us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 832.250us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 13.000s 832.250us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 14.077us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 14.000s 3564.393us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 3564.393us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 3564.393us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 10.000s 3147.597us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 53.914us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1529.016us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 84.941us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 69.914us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 69.914us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 14.000s 3564.393us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 4.000s 636.810us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 10.000s 3147.597us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 4.000s 636.810us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 636.810us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 2.000s 69.914us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 636.810us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 53.000s 1027.210us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 84443773274363119179845303802780997057409039250539006771731766655556535002797 86
UVM_INFO @ 244863525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 84251546475533176721534603409580746655023427784529251500578870137608838911375 86
UVM_INFO @ 39707645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 113735453555560396496598460149252015316045013034772015415005725944946957303629 86
UVM_INFO @ 76107045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 39880775499056979769695863976906845258134163685549573348644122253388221905662 86
UVM_INFO @ 69885035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 64495136531791209389781655154906868196288121512011370141015060784210560501998 86
UVM_INFO @ 26634660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 103275571512684272061420709317467734994583053549436784870375326543378235444233 86
UVM_INFO @ 55500708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 46121695651142120152360831048607452806167248981029681889230897018472494252759 86
UVM_INFO @ 273750384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 88732021679226894097521401944204065811724317497117159758864665915787861663191 86
UVM_INFO @ 147818902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 62053071215273429931046818557654539862715774294914826419907792260019667380657 86
UVM_INFO @ 224016723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 91185272211082953705707667357218407070829162078858092077591041028894896787089 86
UVM_INFO @ 142263118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 51143516071180056335278306784678133374410504359665832581874497657376892653742 86
UVM_INFO @ 204710094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 74504666831476872508638918440712301995779038526500499610329178989977093969053 86
UVM_INFO @ 54132488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 45352921722817827545384887102153756240013234351423076838625973629334628999484 86
UVM_INFO @ 59967502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 22950189674964157008015906388805020055195511646398081572454959387263049185197 86
UVM_INFO @ 50600459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 71677509711671412095015401356648644017158107219042804531880717242994550841191 86
UVM_INFO @ 28939606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 65087048234928201665609502346790576985411674426125061452532575560445911609904 86
UVM_INFO @ 155269215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 85633968119241980135738909419480511409476214050892926486601808702180453152681 86
UVM_INFO @ 127749965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 29612337309255299967202064991345640062637656862585210405779850575903123091149 86
UVM_INFO @ 119670167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 65184882026880832486757700870238813806333473979217675915069650418759308236167 86
UVM_INFO @ 80766795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 67439008283017645840691331859616808878300116336791422316118105097411489754016 86
UVM_INFO @ 117298217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 59410236326998025147131090330413929877787790898589625368816264638586748562448 86
UVM_INFO @ 109582786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 104152422061392248412357471377334524105675216058752458405389610229352764231961 86
UVM_INFO @ 113568969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 63534855366449295973319945184803336438829722839953622147542681268353399686831 86
UVM_INFO @ 378863736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 38426932517129251838944975440909329574055138168594103746626625205764730268512 86
UVM_INFO @ 29536525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---