Simulation Results: ac_range_check

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
98.11%
V2
98.86%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 60.000s 1736.745us 20 20 100.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 74.000s 5807.875us 19 20 95.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 24.000s 189.063us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 160.196us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 55.000s 745.307us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 52.000s 1163.906us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 23.000s 31.916us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 160.196us 5 5 100.00
ac_range_check_csr_aliasing 52.000s 1163.906us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 953.121us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 65.000s 1004.041us 1 1 100.00
stress_all 9 10 90.00
ac_range_check_stress_all 265.000s 42942.763us 9 10 90.00
alert_test 10 10 100.00
ac_range_check_alert_test 30.000s 12.005us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 15.173us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 6.000s 160.638us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 6.000s 160.638us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 24.000s 189.063us 1 1 100.00
ac_range_check_csr_rw 3.000s 160.196us 5 5 100.00
ac_range_check_csr_aliasing 52.000s 1163.906us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 177.943us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 24.000s 189.063us 1 1 100.00
ac_range_check_csr_rw 3.000s 160.196us 5 5 100.00
ac_range_check_csr_aliasing 52.000s 1163.906us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 177.943us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 28.000s 2586.281us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 28.000s 2586.281us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 28.000s 2586.281us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 28.000s 2586.281us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 136.000s 19485.402us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 20.690us 5 5 100.00
ac_range_check_tl_intg_err 14.000s 616.400us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 402.000s 11383.545us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 53.000s 1820.100us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 2 test runs
ac_range_check_stress_all 4903296749573918033984472381095672120202440438046204209645924803657468255174 17920
UVM_INFO @ 7208186948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 60073202318774996219738142673419938264334619587320175964045135248997338157308 4248
UVM_INFO @ 616265071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---