| V1 |
|
100.00% |
| V2 |
|
87.97% |
| V2S |
|
97.56% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.070s | 7261.013us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| alert_handler_csr_hw_reset | 7.650s | 204.419us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| alert_handler_csr_rw | 13.380s | 139.926us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| alert_handler_csr_bit_bash | 385.830s | 25129.742us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| alert_handler_csr_aliasing | 366.950s | 5345.303us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 11.800s | 148.099us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| alert_handler_csr_rw | 13.380s | 139.926us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 366.950s | 5345.303us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 25 | 25 | 100.00 | |||
| alert_handler_esc_alert_accum | 433.100s | 40434.294us | 25 | 25 | 100.00 | |
| esc_timeout | 50 | 50 | 100.00 | |||
| alert_handler_esc_intr_timeout | 99.310s | 6846.965us | 50 | 50 | 100.00 | |
| entropy | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 3481.150s | 356937.855us | 24 | 25 | 96.00 | |
| sig_int_fail | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 91.020s | 1515.796us | 50 | 50 | 100.00 | |
| clk_skew | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.070s | 7261.013us | 10 | 10 | 100.00 | |
| random_alerts | 10 | 10 | 100.00 | |||
| alert_handler_random_alerts | 96.190s | 28339.652us | 10 | 10 | 100.00 | |
| random_classes | 50 | 50 | 100.00 | |||
| alert_handler_random_classes | 94.940s | 3263.972us | 50 | 50 | 100.00 | |
| ping_timeout | 19 | 50 | 38.00 | |||
| alert_handler_ping_timeout | 723.030s | 154846.173us | 19 | 50 | 38.00 | |
| lpg | 92 | 100 | 92.00 | |||
| alert_handler_lpg | 3600.135s | 0.000us | 46 | 50 | 92.00 | |
| alert_handler_lpg_stub_clk | 3602.051s | 0.000us | 46 | 50 | 92.00 | |
| stress_all | 49 | 50 | 98.00 | |||
| alert_handler_stress_all | 4395.410s | 336745.670us | 49 | 50 | 98.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 40.200s | 3372.062us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 20 | 20 | 100.00 | |||
| alert_handler_alert_accum_saturation | 7.280s | 835.856us | 20 | 20 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| alert_handler_intr_test | 2.420s | 16.188us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 36.670s | 373.572us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| alert_handler_tl_errors | 36.670s | 373.572us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 7.650s | 204.419us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 13.380s | 139.926us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 366.950s | 5345.303us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 56.760s | 1352.990us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| alert_handler_csr_hw_reset | 7.650s | 204.419us | 1 | 1 | 100.00 | |
| alert_handler_csr_rw | 13.380s | 139.926us | 5 | 5 | 100.00 | |
| alert_handler_csr_aliasing | 366.950s | 5345.303us | 1 | 1 | 100.00 | |
| alert_handler_same_csr_outstanding | 56.760s | 1352.990us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 450.320s | 5985.642us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 450.320s | 5985.642us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 450.320s | 5985.642us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 450.320s | 5985.642us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 1405.220s | 118352.050us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| alert_handler_tl_intg_err | 139.980s | 5586.076us | 25 | 25 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| alert_handler_tl_intg_err | 139.980s | 5586.076us | 25 | 25 | 100.00 | |
| sec_cm_config_shadow | 20 | 20 | 100.00 | |||
| alert_handler_shadow_reg_errors | 450.320s | 5985.642us | 20 | 20 | 100.00 | |
| sec_cm_ping_timer_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.070s | 7261.013us | 10 | 10 | 100.00 | |
| sec_cm_alert_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.070s | 7261.013us | 10 | 10 | 100.00 | |
| sec_cm_alert_loc_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.070s | 7261.013us | 10 | 10 | 100.00 | |
| sec_cm_class_config_regwen | 10 | 10 | 100.00 | |||
| alert_handler_smoke | 63.070s | 7261.013us | 10 | 10 | 100.00 | |
| sec_cm_alert_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 91.020s | 1515.796us | 50 | 50 | 100.00 | |
| sec_cm_lpg_intersig_mubi | 46 | 50 | 92.00 | |||
| alert_handler_lpg | 3600.135s | 0.000us | 46 | 50 | 92.00 | |
| sec_cm_esc_intersig_diff | 50 | 50 | 100.00 | |||
| alert_handler_sig_int_fail | 91.020s | 1515.796us | 50 | 50 | 100.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 3481.150s | 356937.855us | 24 | 25 | 96.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 24 | 25 | 96.00 | |||
| alert_handler_entropy | 3481.150s | 356937.855us | 24 | 25 | 96.00 | |
| sec_cm_esc_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_sparse | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_fsm_local_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_fsm_global_esc | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| sec_cm_accu_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| sec_cm_esc_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_ctr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| sec_cm_ping_timer_lfsr_redun | 5 | 5 | 100.00 | |||
| alert_handler_sec_cm | 36.030s | 1878.112us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 5 | 10 | 50.00 | |||
| alert_handler_stress_all_with_rand_reset | 750.140s | 13404.355us | 5 | 10 | 50.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state | 26 test runs | |||
| alert_handler_ping_timeout | 93087779062905787347118021171008741988503298033323722038226120572397146063909 | 93 |
UVM_INFO @ 2460573334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 82069125864305221834569042055235211212934520115549020443049982066832692849997 | 87 |
UVM_INFO @ 3519730509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 28471367778638826515977758801931679694626914026822596844929061668074693795273 | 87 |
UVM_INFO @ 1400758655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 70650657044543960701853566259608330830868332169254612392056232536904554646419 | 84 |
UVM_INFO @ 3902068501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 58126031116114017306669111837060447874350237732309222757491889286939178058318 | 102 |
UVM_INFO @ 15084921360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 7025843702073107799304627783035125389168867267802094634857811479212490834712 | 97 |
UVM_INFO @ 2238528257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 8139825158429613800700980790541380928659150453136521725389661895068811305319 | 139 |
UVM_INFO @ 6138188460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 107185276644692971061059751965955744477166611607085549254851807712130145093103 | 112 |
UVM_INFO @ 3993274922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 107690743888766765068222279135348995023937095472156513548113537543900116848874 | 87 |
UVM_INFO @ 6204716906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 52646612030489416533731158001057453155573604745403126962003653403757761928542 | 90 |
UVM_INFO @ 7171319853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 73749106611143971712627242102287386077816340125813395212278758427555426798768 | 105 |
UVM_INFO @ 10719122460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 73198912930695511711967743289935556564054414790396389848658413776219002489345 | 84 |
UVM_INFO @ 1341876216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 56459756608013838576410289537056497716603834878098350610140358788148919498737 | 96 |
UVM_INFO @ 17503562320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 63608919808153967950393257326671940275913757737108638391998238911946259245945 | 136 |
UVM_INFO @ 12088203462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 50785790535206656374600573383497876197326067294099429192403735442033796541484 | 90 |
UVM_INFO @ 8599426266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 31437096898904050053828261816715944031363335108190118859604800347214249518765 | 84 |
UVM_INFO @ 892608965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 78643726899421358036756936411777329446061372625599053915720838457541946647667 | 90 |
UVM_INFO @ 1575509987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80563300104219224982755943205705938152827672135674474876955358155722957924012 | 105 |
UVM_INFO @ 8756567178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 71934442135782060117649398637882908677456258525639978231366250589869208398645 | 93 |
UVM_INFO @ 6745086425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 16584999729117714588395009743997441012477940795045611421671605925198560470848 | 106 |
UVM_INFO @ 18469292686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 80201054569374261976978480472027775934048871670305365753786029787510621541592 | 126 |
UVM_INFO @ 28665484278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 97420111102827538221753875194849814683030212113436592143808945933063309778003 | 93 |
UVM_INFO @ 2854248832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 72522634739885248904540026047611052680098323405548848633243661370558560609217 | 105 |
UVM_INFO @ 25207480524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 103252067683177067100306175687633956398976772443547131371774011881720805574896 | 96 |
UVM_INFO @ 1870281128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 51150037522620585857793924465907315347248017422757891865055118761051675048857 | 97 |
UVM_INFO @ 12646856067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 7725580206723605298599187412428573284618214782799539027216093236943888239924 | 96 |
UVM_INFO @ 2864570583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped | 20 test runs | |||
| alert_handler_entropy_stress | 48738363941560435069554219699722833673864352015442997131853641935064167469965 | 204 |
UVM_INFO @ 542789732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 68699687378307741807770266427730852987060699848255776740860374820440433704701 | 224 |
UVM_INFO @ 185801220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 18317578021506840215976153557861737060136039848914521985304888905763032031690 | 216 |
UVM_INFO @ 3372062388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 54695131957511277178534115213155990981401276601957904740518530132167886982964 | 226 |
UVM_INFO @ 159435361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 37240918393223833784393118261251348647525788368607459935942155820965286844726 | 222 |
UVM_INFO @ 2520350353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 113731853170684309715571340689072764667557021961924231062269241414661991810033 | 220 |
UVM_INFO @ 1063161062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 53918521600979744906570608279669829438018156029672396582525034157873266575481 | 224 |
UVM_INFO @ 2519976959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 33962492112805064201041310823561938362153028452750510579742202107541956570272 | 224 |
UVM_INFO @ 918829604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 100969278820946400887326803854410149871417589249128268671495766538931492072484 | 200 |
UVM_INFO @ 714064954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 114388786754503278474528740964783531020315870406108824067583247143559504611719 | 218 |
UVM_INFO @ 175460315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 28960072688362338418234187939382312623064198723678602438426509361924961904538 | 168 |
UVM_INFO @ 82461230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 100027753895962188804312791987298045405907435347904475183912003615796813372409 | 182 |
UVM_INFO @ 217540753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 62928636568984230657578432527482458685787564411603953827142248018261170776884 | 194 |
UVM_INFO @ 858628725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 37877241414897871623235985963502298410118364463931471895249263740566519377450 | 184 |
UVM_INFO @ 193133620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 77240278524682683544819615876297919072671204901429945105217972563241162344052 | 164 |
UVM_INFO @ 1165577718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 41015463091399428626656880622515981578821084550240796600328497170235988142624 | 212 |
UVM_INFO @ 120930794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 51299866050553949946371534463321661330883725137472445468518697092810947281643 | 224 |
UVM_INFO @ 140525987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 78649382742672429606967887215748395232004815014802527585220884817402027395037 | 218 |
UVM_INFO @ 768320427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 11368097258555966502172560607608625966884673047583102746640347287380004812384 | 190 |
UVM_INFO @ 124490595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_entropy_stress | 31167669771317104688578206004217752743314231197591562063497615224549892897147 | 182 |
UVM_INFO @ 129223151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 7 test runs | |||
| alert_handler_lpg | 44979529430204013436182501867430751932069678358288735014834813434438298027266 | None | ||
| alert_handler_lpg | 114040339539930291521770717437333048682015057608593753705552599819359558643736 | None | ||
| alert_handler_lpg | 28739551160088807845019120195326880190738787856579205875594972195624790788171 | None | ||
| alert_handler_lpg_stub_clk | 101958237103834251971127058648329742694606070727185134580139407566548885596114 | None | ||
| alert_handler_lpg_stub_clk | 115292808027701382730228270284373126037603085788553250856829030463811864316412 | None | ||
| alert_handler_lpg_stub_clk | 18937733380850562938076121361407864745678109513211010756150828322157748777444 | None | ||
| alert_handler_lpg | 14434342079107050796426709280076836099248515313975927242554923627378173822122 | None | ||
| UVM_ERROR (alert_handler_scoreboard.sv:608) scoreboard [scoreboard] Register/crashdump mismatch. loc_alert_cause[*] is * in the crashdump and * in the register model. | 5 test runs | |||
| alert_handler_ping_timeout | 42517631114997559203667400584416687834482592591355726787303396233874193020990 | 80 |
UVM_INFO @ 1760103691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 33934858838544129045878113737084383942699312678754968806566478864792144266050 | 80 |
UVM_INFO @ 1415377746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 59163817799590243835158552355197155508302159304901472412688921182616073088364 | 80 |
UVM_INFO @ 396980112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 113726299806696845008741794701370615411231730144359857610590736163361315792548 | 80 |
UVM_INFO @ 1622352463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_ping_timeout | 42478406274520669009208770106642333441847136902735699533138402929486112289257 | 80 |
UVM_INFO @ 884303475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 5 test runs | |||
| alert_handler_stress_all_with_rand_reset | 74605788222095059900015214970449066873896406791197587862074156597117843004752 | 123 |
UVM_INFO @ 2150319716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 17405170967164072798086977424039715342321859049252238415259601026810440608141 | 83 |
UVM_INFO @ 721093080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 92897705318567991564170655989317445889612123135475947919219085398513231353511 | 145 |
UVM_INFO @ 4406717634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 97412964937078007567889913866225104500090700864360424515939154505028724372771 | 137 |
UVM_INFO @ 2302715967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| alert_handler_stress_all_with_rand_reset | 35038001166254670395281590926208336105140265709132312027089397220068792595512 | 83 |
UVM_INFO @ 194000286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classc_accum_cnt | 1 test run | |||
| alert_handler_entropy | 14932626666378282785186229049301495516501687797896466173556080219003666963678 | 80 |
UVM_INFO @ 356937855207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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| UVM_ERROR (alert_handler_scoreboard.sv:490) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: alert_handler_reg_block.classb_accum_cnt | 1 test run | |||
| alert_handler_lpg_stub_clk | 39032633307608009426660419413648191842449548782813616750809644735234810411883 | 80 |
UVM_INFO @ 107485225988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 1 test run | |||
| alert_handler_stress_all | 12013135180323374923032058529210951237366028738265516576439275959143901683302 | 246 |
UVM_INFO @ 407370819722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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