Simulation Results

Simulation Results: clkmgr

03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
83.30 %

code
79.74 %

assert
94.01 %

func
76.15 %

line
91.49 %

branch
93.99 %

cond
88.22 %

toggle
100.00 %

FSM
25.00 %

Validation stages

V1		73.91%
V2		68.38%
V2S		30.48%
V3		0.00%

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.500s	164.846us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.550s	45.870us	1	1	100.00
csr_rw				3	5	60.00
	clkmgr_csr_rw	2.610s	124.900us	3	5	60.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	1.850s	49.520us	0	1	0.00
csr_aliasing				0	1	0.00
	clkmgr_csr_aliasing	1.100s	6.465us	0	1	0.00
csr_mem_rw_with_rand_reset				3	5	60.00
	clkmgr_csr_mem_rw_with_rand_reset	2.390s	39.301us	3	5	60.00
regwen_csr_and_corresponding_lockable_csr				3	6	50.00
	clkmgr_csr_rw	2.610s	124.900us	3	5	60.00
	clkmgr_csr_aliasing	1.100s	6.465us	0	1	0.00

80/117 passed

68.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	2.310s	100.649us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	3.170s	154.421us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	3.070s	161.727us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.500s	164.846us	10	10	100.00
frequency				1	10	10.00
	clkmgr_frequency	1.690s	54.907us	1	10	10.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.000s	18.583us	0	10	0.00
frequency_overflow				1	10	10.00
	clkmgr_frequency	1.690s	54.907us	1	10	10.00
stress_all				0	10	0.00
	clkmgr_stress_all	9.580s	596.174us	0	10	0.00
alert_test				10	10	100.00
	clkmgr_alert_test	3.090s	149.707us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	16.010s	1633.624us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	16.010s	1633.624us	25	25	100.00
tl_d_outstanding_access				4	12	33.33
	clkmgr_csr_hw_reset	1.550s	45.870us	1	1	100.00
	clkmgr_csr_rw	2.610s	124.900us	3	5	60.00
	clkmgr_csr_aliasing	1.100s	6.465us	0	1	0.00
	clkmgr_same_csr_outstanding	1.950s	72.391us	0	5	0.00
tl_d_partial_access				4	12	33.33
	clkmgr_csr_hw_reset	1.550s	45.870us	1	1	100.00
	clkmgr_csr_rw	2.610s	124.900us	3	5	60.00
	clkmgr_csr_aliasing	1.100s	6.465us	0	1	0.00
	clkmgr_same_csr_outstanding	1.950s	72.391us	0	5	0.00

V2S

32/105 passed

30.48 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				3	30	10.00
	clkmgr_sec_cm	113.940s	10008.492us	3	5	60.00
	clkmgr_tl_intg_err	2.420s	95.075us	0	25	0.00
shadow_reg_update_error				15	20	75.00
	clkmgr_shadow_reg_errors	2221.590s	200000.000us	15	20	75.00
shadow_reg_read_clear_staged_value				15	20	75.00
	clkmgr_shadow_reg_errors	2221.590s	200000.000us	15	20	75.00
shadow_reg_storage_error				15	20	75.00
	clkmgr_shadow_reg_errors	2221.590s	200000.000us	15	20	75.00
shadowed_reset_glitch				15	20	75.00
	clkmgr_shadow_reg_errors	2221.590s	200000.000us	15	20	75.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.270s	22.962us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	2.420s	95.075us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				1	10	10.00
	clkmgr_frequency	1.690s	54.907us	1	10	10.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.000s	18.583us	0	10	0.00
sec_cm_meas_config_shadow				15	20	75.00
	clkmgr_shadow_reg_errors	2221.590s	200000.000us	15	20	75.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	2.220s	85.047us	10	10	100.00
sec_cm_jitter_config_mubi				3	5	60.00
	clkmgr_csr_rw	2.610s	124.900us	3	5	60.00
sec_cm_idle_ctr_redun				3	5	60.00
	clkmgr_sec_cm	113.940s	10008.492us	3	5	60.00
sec_cm_meas_config_regwen				3	5	60.00
	clkmgr_csr_rw	2.610s	124.900us	3	5	60.00
sec_cm_clk_ctrl_config_regwen				3	5	60.00
	clkmgr_csr_rw	2.610s	124.900us	3	5	60.00
prim_count_check				3	5	60.00
	clkmgr_sec_cm	113.940s	10008.492us	3	5	60.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.320s	28.921us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	81.280s	7651.970us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				25 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	30506525275161458797390624741750825606361724702942496786821554492501093668958	75	UVM_INFO @ 9028900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_aliasing	21149980768519412447262087937050761688431182426552282993373582483420831666657	75	UVM_INFO @ 6464737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	64024574523188897193952779928125902345865277327316118507390900817109431185887	82	UVM_INFO @ 6513650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	79743011156588242280811418911018934167026605776594433638042062127935110633937	75	UVM_INFO @ 12328542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	106675907671303860424251731867166965078207074861987559296529483084733062138258	81	UVM_INFO @ 11749127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	64607298863006883844435815361762492953167255406501683814520009949241510305520	75	UVM_INFO @ 3942531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	113561279625972367480687445415977019325174456427624646543850761867229277365810	87	UVM_INFO @ 7123180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	3059397039640139717214868089816154894647045242429490276456941935892716910451	75	UVM_INFO @ 15873790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	45631389806320831745691878772896456615302524138831550007189571789217253931455	85	UVM_INFO @ 14891232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	63326229119480366953786159181729867975112346353510522336698373838323908618123	75	UVM_INFO @ 2526040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	105961148093908399803731161875821485776144342063923115148616741867495178690735	85	UVM_INFO @ 4446940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	87008262513722661397426223619724890151038635936484550826600175964780955352176	75	UVM_INFO @ 6281136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	26977195602573603689703143235492421928658614424761531421426632014754035414100	89	UVM_INFO @ 27190243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	62847413570150961859335322896941153450654799990561859128787425367398534098585	85	UVM_INFO @ 4822290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	28988098353288442092593097522279779004510298050166123405860942806879157491619	75	UVM_INFO @ 12724580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	79676208969201931177561741087792942465396195837692669990785814718844954133446	75	UVM_INFO @ 8540473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	65134466886297542395414130025312816646883245866681329995641234981427310253808	78	UVM_INFO @ 2434536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	37640873733252645267768744148395230583413824896692311041582620865206217570359	75	UVM_INFO @ 15864346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	63874489920250333185922378265560298298741408498963969804002187250489295999304	75	UVM_INFO @ 4987348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	33338011997422089293435564274714568396290471606214791573201895076575104993058	75	UVM_INFO @ 7084418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	11285217452553200623930158760619388683986341656749515169824357713978873832750	78	UVM_INFO @ 7138258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	87171090992240782935575586568200829470147224389380058386113046757615895202434	93	UVM_INFO @ 7726365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	20459243142750202864524057193418900679489407914256751516915134685344030997257	75	UVM_INFO @ 22961926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	17871193465394534558858341193770037329031017454755317610351437216417535356163	88	UVM_INFO @ 7742204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	78208254872263432042218545055508937694229486024002973472816680423465993828488	102	UVM_INFO @ 37545368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				25 test runs
	clkmgr_tl_intg_err	16625051396480115817088607066583473082368281478752219750215873084080102712252	93	UVM_INFO @ 57771473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	35948893214061019101399706036345016845633595663739669710798441621187365922038	75	UVM_INFO @ 8913250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	48934934381650497137622597524714285415779967722621626625814630688762237282631	75	UVM_INFO @ 9377838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	94896942060531734809365168645270778150807142403519965791843377795669956986326	75	UVM_INFO @ 3895288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	90883536777187463984299483686580452183520294901808903909262589013320334752741	100	UVM_INFO @ 78760245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	92710692296685084272975273801055140452954650175934613553239197060659357970601	99	UVM_INFO @ 35004380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	71255046089411921123694008628617618482000161207029723181260751107438658972621	80	UVM_INFO @ 3795327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	27388303965815178278782740954565951636523087656965381019183616648853242346762	82	UVM_INFO @ 29186265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	37548125415894683882366646057583016056725258312810241396413035822268028749051	75	UVM_INFO @ 5542479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	106070151456760685586464861633393777860783549495952872878946428620409335720446	82	UVM_INFO @ 3329537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	12191988974260300921249647407960733236180170777723817491587600373771953921471	80	UVM_INFO @ 3221542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50063729584911162640804494665474922439453360469121629690571734293289708671730	97	UVM_INFO @ 14447107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	87307918516894224788817747196802044460451383308245218273575216467557046803066	103	UVM_INFO @ 22826237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	41331820977650758083143156365430764696181084089020188669318461130719117347257	93	UVM_INFO @ 8417604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	26900484238495129984424489328177267962071286909378555062094617438324324328006	75	UVM_INFO @ 6305297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	7678458273983259569004406240298900272513141427107425724646644631605329086473	100	UVM_INFO @ 12715470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	61728692443151085602972809454220514456438596989452258062789889111521900321462	75	UVM_INFO @ 2569498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	92415702180199591821958998108248460391899998443726499597649969303733452049844	75	UVM_INFO @ 3218844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	110932229004503021818287464739032636355690180813134622760558878173596414711434	75	UVM_INFO @ 19849786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	70333397520585151297844847928051692752286224116384203064353344485200568522605	101	UVM_INFO @ 95074691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	63429326987881585009050688267458629342857481996767449983358698594240872106317	75	UVM_INFO @ 3618058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	96644707252770185019093872752198061687611625537402202506474218447720360994041	101	UVM_INFO @ 47577265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	93623192081610473028434581626536452503434527619203952302067266026174809971640	95	UVM_INFO @ 19342270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	96881966647341032687746546903142400913887949321643543632073092866136186623196	87	UVM_INFO @ 3888763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	32569394051795075118241170550306374300839097496662020391997764999870222662001	75	UVM_INFO @ 3712267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				22 test runs
	clkmgr_frequency_timeout	56651094329524829616608199160887061404930207851466522281060271794099189966100	77	UVM_INFO @ 3432615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	82029988098883910833997289225825317791713304326351742984373317885775074001849	78	UVM_INFO @ 29717875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	54511253167859634049469655266343830089466837210700326852625356002676963126240	78	UVM_INFO @ 4914460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	79138546996385365893923282776113231790919616457945611191061331853144208022367	78	UVM_INFO @ 2400232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	18269584156614218699875197998593785493489111824798682662367297329356533953164	78	UVM_INFO @ 5104370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	5565530458693009760269129902356317266361704182108250232584996402377339969060	82	UVM_INFO @ 3707910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	20728902150144426708190309664346775226635779800493425349418534969605106857547	125	UVM_INFO @ 596173864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	1339217353269973821303646979451397334410513360015326011039090166067550922518	83	UVM_INFO @ 3603271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	103047292802694852741955517893893354230158629292955947873575201511487903547897	90	UVM_INFO @ 38419627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	25495314053636743032151952600242271775743000472667314335913912762486944490438	201	UVM_INFO @ 55511554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	8676709570428765781936365610370579584278375422936049767543129217588035019042	78	UVM_INFO @ 4098776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	114300185554032551537515112219744560338613545006702406568510187460814110872553	208	UVM_INFO @ 103772001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	35645174062660167262914771356507718577917607311697349325236457731511039486850	77	UVM_INFO @ 22566952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	105689149064515841027908886226791228072269662921968648861650603749731819200958	83	UVM_INFO @ 3428865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	71184916743815709388288449204049474784443180303824977175664677469170353133489	79	UVM_INFO @ 3934134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	76333302562264464663026419148529422098004616585250362227279604221999374290519	113	UVM_INFO @ 211227502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	65820295009957097755215476951207617879015422244941610890073308066718548539525	77	UVM_INFO @ 2217067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	77709912186469973618636602563938843991779798426816097665469075977910305406574	85	UVM_INFO @ 169056084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	53494274211147571876967153849699417180654668836561322943504451756108579433173	78	UVM_INFO @ 18582833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	8667532216666077181525677290846204902653816244610084588710245452914770482556	77	UVM_INFO @ 6639980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	88619148746037694535690382554456492923234312747507071809062816464812305446727	78	UVM_INFO @ 1722593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	88017761350851440327225002776511514936628811665084375128292264237820716196243	78	UVM_INFO @ 8683132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				17 test runs
	clkmgr_frequency	94853475024372052199268092966062831009559552091795456395219933533844421953216	78	UVM_INFO @ 10219382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	3562511016769175333082494150639479065849581501067427471340796839251108685232	231	UVM_INFO @ 7651970236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	1896759269034649595322829163621937033048302830467506547278993814088925126507	75	UVM_INFO @ 15414995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	50053275833676677828845895789538113824902315985747192304062378448217288910677	78	UVM_INFO @ 6160142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	69159580996608003297542392701949709656806697214158894542741903928465188498245	130	UVM_INFO @ 24632651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	91962668582595887519865311638285130552872750218989171017392619543474870228064	75	UVM_INFO @ 7054444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	32618826244477626729034817111284760606519670502769720969569322109038369116394	84	UVM_INFO @ 50891637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	48494989115842003252371070536868970631787324582401529955244392257907940138969	75	UVM_INFO @ 8434893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	74515915192275478016163376492962191021584237700476519901119473078268211102504	82	UVM_INFO @ 100344464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	33942523723878983410922377478112841001095513209076474086710773244637919743090	75	UVM_INFO @ 11574236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	95503340355133386634250385886597658522023907955888334155345256650165585504665	81	UVM_INFO @ 34687553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	113595289436192141247376879046388694855274408049343849349311509234017340971785	75	UVM_INFO @ 6432998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	30127923128966608334956388475884482902926930088768851064942377843106595663574	168	UVM_INFO @ 662592776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	47173806497499313721236508377466827355288066613167403906671160026015956672495	78	UVM_INFO @ 28485304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	106569205656246400273350851380914386056513523442414954738712082998686925722581	78	UVM_INFO @ 8717122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	81505846143306444022686854492495650509305071810451524524743471463961302430908	75	UVM_INFO @ 5023325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	29814804648213250175601184968010199276002686222908836797061866201572618299260	144	UVM_INFO @ 49927099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				8 test runs
	clkmgr_regwen	25416038322577918951459615510725932996597867029977124308408401615658348049549	74	UVM_INFO @ 4009679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	58193871979877069276210891334410356343456289480285661801689432700725923028574	74	UVM_INFO @ 15258449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	79761203873143231170485591665300154924820263634608209281355191560947656143089	74	UVM_INFO @ 17788530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	21100138625722228142090334941546986828009296914880642317504655094026543039887	74	UVM_INFO @ 28921282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	71092484783270722456197051415347368553366177335127181128364981506910945606529	74	UVM_INFO @ 3396586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	64125540972548685399839383261805829898796622764189750087372566893340444533943	74	UVM_INFO @ 2742005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	41545473984078886275050441328494248405634628202742111576357560434270187332222	74	UVM_INFO @ 12754875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	85896744418186006374838492492216662565071708229698864616063041830323720831815	74	UVM_INFO @ 2895969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	52662142808735766540347262610314080296387822355644304054048746128414019512074	75	UVM_INFO @ 55717780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	47589147949936153455135413120257050425645454220772105303135000325936057704008	75	UVM_INFO @ 72390539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	14386004892834574020924222029221888264588485025648326626921402691698973500191	75	UVM_INFO @ 13581107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	97986007926307710956915305200223552371584179145127594400509886123524032059572	75	UVM_INFO @ 13135612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	45260596676304321017271527667260641120006857183276940582551945619112390753032	75	UVM_INFO @ 21818485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				5 test runs
	clkmgr_shadow_reg_errors	18054760005277063331987182162419847157141393699079733290854726222498084124902	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	105646682910626178528511774267663342222727732509080322036986501593531136649365	76	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	107922731282079510549892277247009267472484810780182782405708539026148568301649	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	70134998070265159938775757702711215508159661328163661668712111448702616506566	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	11709699108464394420257414137059024295618544755121132779389619442863432462851	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				2 test runs
	clkmgr_regwen	36307794316469148289059766105360878487479003214515511322820151179259508672466	74	UVM_INFO @ 7681637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	74912697837802496029423606451179215319816554967000313850552751965222658275537	79	UVM_INFO @ 8514324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				1 test run
	clkmgr_sec_cm	70887640262489480400825333299468649328121225647579213491381534903717008773967	80	UVM_INFO @ 10008492298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	61294947931451162978845522651069842152913694623671212664083306401349487624663	75	UVM_INFO @ 49520397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				1 test run
	clkmgr_sec_cm	58339865731990764912285387444233252888461405217512805968505074082276932855650	139	UVM_INFO @ 95029616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---