Simulation Results: csrng

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.66 %
  • code
  • 96.20 %
  • assert
  • 97.16 %
  • func
  • 90.62 %
  • block
  • 98.53 %
  • line
  • 99.54 %
  • branch
  • 96.38 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.24%
V2S
99.46%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 5.000s 383.193us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 31.000s 27.151us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 32.000s 26.693us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 66.000s 1439.865us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 34.000s 81.609us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 34.000s 196.600us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 32.000s 26.693us 5 5 100.00
csrng_csr_aliasing 34.000s 81.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
alerts 500 500 100.00
csrng_alert 41.000s 3237.936us 500 500 100.00
err 500 500 100.00
csrng_err 32.000s 47.821us 500 500 100.00
cmds 2 25 8.00
csrng_cmds 45.000s 3973.857us 2 25 8.00
life cycle 2 25 8.00
csrng_cmds 45.000s 3973.857us 2 25 8.00
stress_all 25 25 100.00
csrng_stress_all 890.000s 78125.833us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 30.000s 44.302us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 32.000s 12.305us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 13.000s 981.413us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 13.000s 981.413us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 31.000s 27.151us 1 1 100.00
csrng_csr_rw 32.000s 26.693us 5 5 100.00
csrng_csr_aliasing 34.000s 81.609us 1 1 100.00
csrng_same_csr_outstanding 4.000s 25.999us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 31.000s 27.151us 1 1 100.00
csrng_csr_rw 32.000s 26.693us 5 5 100.00
csrng_csr_aliasing 34.000s 81.609us 1 1 100.00
csrng_same_csr_outstanding 4.000s 25.999us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 10.000s 742.619us 5 5 100.00
csrng_tl_intg_err 15.000s 794.334us 25 25 100.00
sec_cm_config_regwen 23 30 76.67
csrng_regwen 16.000s 13.260us 18 25 72.00
csrng_csr_rw 32.000s 26.693us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 41.000s 3237.936us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 890.000s 78125.833us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
csrng_sec_cm 10.000s 742.619us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
csrng_sec_cm 10.000s 742.619us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
csrng_sec_cm 10.000s 742.619us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
csrng_sec_cm 10.000s 742.619us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
csrng_sec_cm 10.000s 742.619us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 41.000s 3237.936us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 890.000s 78125.833us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 41.000s 3237.936us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 15.000s 794.334us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
csrng_sec_cm 10.000s 742.619us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
csrng_sec_cm 10.000s 742.619us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 38.000s 389.019us 200 200 100.00
csrng_err 32.000s 47.821us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 20 test runs
csrng_cmds 111108633532982949556304109735163656175688900652151053796614290268049024565865 100
UVM_INFO @ 135817429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 84382400090998098976739609597305889369126891030147215043815256750435093803934 100
UVM_INFO @ 217293618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 17937484769511118111969336522027990988720752111615320534393240370349849045297 100
UVM_INFO @ 79420891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 67703832553277624353886528811743672936182077369052722485368478401501441770501 110
UVM_INFO @ 266727229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 60862905917212499065745282253679813318245107198190432932171569799109761370527 100
UVM_INFO @ 99912114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 95479396543856917045633552156852013744838976937372309309728558740661581092677 100
UVM_INFO @ 492555194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 97153726017298601452089673485329911632745405093436053237385859632510276159796 100
UVM_INFO @ 52178967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 61576021019039047454496281271744432688221095723483077316978856537242759124411 120
UVM_INFO @ 1142634973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 31972966527166182401321189854508742670206882405971681581916373711233756682145 100
UVM_INFO @ 177809592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 9734880337312519204395159041971524084957378345191368934776113173387269819203 100
UVM_INFO @ 56325862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 81073432151272865649441049244188585258364347382899399658317173316876406730326 100
UVM_INFO @ 12706179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 59523172548982453921869127366524878907348232554195292567088990608070100783113 100
UVM_INFO @ 136303803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 113021175549814000070739110880016018287768694178829880207118223949923205339096 100
UVM_INFO @ 117311324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 27378695781343525065482164980941531442701696316114033663852217785968182472629 100
UVM_INFO @ 314425991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 84391005820173451370467474228281239608163754557847965036418510166061570818217 100
UVM_INFO @ 113300061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 15929354801147477960384005030436511193398921861554723327990136718416228279554 100
UVM_INFO @ 41991110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 108334977493972353844152473069483972039038432611774692540830810609139344514026 100
UVM_INFO @ 315585333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 84528090505416931697194525708873402909554105856172978878454325754540632030464 100
UVM_INFO @ 253479248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 18929862457088327770398388663170235608482173519913390217030969854854938819304 100
UVM_INFO @ 339436438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 19542408289903803065418997561861759613899626296571110406261048845886419506216 100
UVM_INFO @ 46290734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 5 test runs
csrng_stress_all_with_rand_reset 16653035130769196617760151405969226845114244190843911750752110882793041461267 None
csrng_stress_all_with_rand_reset 80311928080436924975292967070298363097747400601997183291648708410602647654986 None
csrng_stress_all_with_rand_reset 41223115220142815278860738662907885449693434629979984201742039434552768706288 None
csrng_stress_all_with_rand_reset 37662540582120960256728134252383789208361613833825502434693158032661390726960 None
csrng_stress_all_with_rand_reset 73901549974170886719969805923099180577814609879325570938375580974519196423753 None
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 5 test runs
csrng_regwen 42355149444165728233615770872578159143202330720901576330855737646441806812138 99
UVM_INFO @ 3329239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 100869794305192891721531528608744531915186287132496499595280232232212951737908 99
UVM_INFO @ 1430593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 49319012667465760321902255781360484422667640349971564547181686517625915284497 99
UVM_INFO @ 11273206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 29596610086163195640470651234206506654835730287739719738229798062471789282614 99
UVM_INFO @ 2803287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 88649557698954756290647865444893879721284672786555938764782118498358485557556 99
UVM_INFO @ 12600416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 3 test runs
csrng_stress_all_with_rand_reset 37554245300613511938040927110789520356340512451146525383800460820684614231583 249
UVM_INFO @ 6159164222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 98686139544450447162891222291327364290763881633888293441984049844880409682077 136
UVM_INFO @ 895970920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 75550378374423583831259638948890727872992264198179785599424429159338540019061 111
UVM_INFO @ 118851263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 2 test runs
csrng_regwen 43051602463967712349178164286136272037605163832499986193655654699240223825724 99
UVM_INFO @ 13260085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 59270431810731893744164148732837829678558077451473110444227328848764385298176 99
UVM_INFO @ 39111533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 1210342319986049646661637604034235316217446451410862319711690377900560883197 154
UVM_INFO @ 1886146277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
csrng_cmds 15994667018972908157238056043697807613157940142500884046422621677110963248684 109
UVM_INFO @ 8498378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 1 test run
csrng_cmds 29620896338666729856200422831114995128432228535115147934979776437532774511505 103
UVM_INFO @ 71012738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:640) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [*] vs * [*]) 1 test run
csrng_cmds 84532886707730574917299380460297753438893679826357943989904593888401985863059 109
UVM_INFO @ 55563969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---