Simulation Results: edn/edn0

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.23 %
  • code
  • 95.28 %
  • assert
  • 98.67 %
  • func
  • 58.74 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.86%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 19.060us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 57.289us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 21.957us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 424.727us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 117.444us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 237.503us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 21.957us 5 5 100.00
edn_csr_aliasing 2.000s 117.444us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 99 100 99.00
edn_genbits 286.000s 10002.110us 99 100 99.00
csrng_commands 99 100 99.00
edn_genbits 286.000s 10002.110us 99 100 99.00
genbits 99 100 99.00
edn_genbits 286.000s 10002.110us 99 100 99.00
interrupts 20 20 100.00
edn_intr 3.000s 21.025us 20 20 100.00
alerts 200 200 100.00
edn_alert 3.000s 77.076us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 59.794us 100 100 100.00
disable 88 100 88.00
edn_disable 2.000s 20.677us 50 50 100.00
edn_disable_auto_req_mode 15.000s 500.000us 38 50 76.00
stress_all 30 30 100.00
edn_stress_all 9.000s 400.597us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 26.438us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 40.865us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.000s 52.287us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.000s 52.287us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 2.000s 57.289us 1 1 100.00
edn_csr_rw 2.000s 21.957us 5 5 100.00
edn_csr_aliasing 2.000s 117.444us 1 1 100.00
edn_same_csr_outstanding 2.000s 103.974us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 2.000s 57.289us 1 1 100.00
edn_csr_rw 2.000s 21.957us 5 5 100.00
edn_csr_aliasing 2.000s 117.444us 1 1 100.00
edn_same_csr_outstanding 2.000s 103.974us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 9.000s 2383.864us 5 5 100.00
edn_tl_intg_err 4.000s 150.118us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 27.049us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 77.076us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.000s 2383.864us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.000s 2383.864us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 9.000s 2383.864us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 9.000s 2383.864us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 77.076us 200 200 100.00
edn_sec_cm 9.000s 2383.864us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 77.076us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.000s 150.118us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 90.000s 16296.532us 25 30 83.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 8 test runs
edn_disable_auto_req_mode 75060053834013751631281722327254525734363437809033707899899427381556529275924 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 24010025883073508871974888227999493153461993153210601661489943984755968626217 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 13977688657915397745462260812309080522875847122829532713141982930206248506037 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 50676688588299757219182804856656958096053172843406650129151232079773253479662 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 57222831922601532255522143189555199979774212603056490970814907443334524470951 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 90003431174297891275715325272594104245617892350823596619122861147785319782635 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 64630567120516510021369094386675769787187456552458531672712767006310262250115 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 16038999600643509160211609132040705632353954212121027329167677597168587817945 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 57277038720691395992780395854478290821661473033472078515471874972424818891642 154
UVM_INFO @ 356205263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 99283202005255996972350741808343651417155605511088635456915915415813990949623 220
UVM_INFO @ 1810425869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 13773931242770510745608530829873428078631926959532907081515621485228003452982 307
UVM_INFO @ 2276821772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 82481097023908921165397983646346237236264485227474195560182542515519039993599 244
UVM_INFO @ 1080429815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 83117526003383713138037488999463403329705956516095523236423011593812088638478 153
UVM_INFO @ 118205694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 4 test runs
edn_disable_auto_req_mode 102019875657057858191417308273190432437249828075457471518433676696524218627420 103
UVM_INFO @ 33684506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 21466140913390105827275537720691940569881428978955741699259273172349790534570 103
UVM_INFO @ 119322076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 10580881618631337373627317584806657598470863319628137279675575934574042391476 103
UVM_INFO @ 27756243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 105079387197705590622647592256807275568536859294601118422892694912791547724829 103
UVM_INFO @ 22281226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout edn_reg_block.sw_cmd_sts.cmd_ack (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 1 test run
edn_genbits 63591514912380300788511922553942925924097725425682633587735559696938417127683 98
UVM_INFO @ 10002110114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---