Simulation Results: edn/edn1

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.77 %
  • code
  • 96.17 %
  • assert
  • 98.70 %
  • func
  • 92.44 %
  • line
  • 98.41 %
  • branch
  • 94.16 %
  • cond
  • 94.38 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
98.68%
V2S
99.57%
V3
76.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.290s 19.245us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.140s 28.857us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.080s 14.969us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.220s 846.339us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.010s 43.445us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.510s 60.463us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.080s 14.969us 5 5 100.00
edn_csr_aliasing 2.010s 43.445us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 67.360s 4979.410us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 67.360s 4979.410us 100 100 100.00
genbits 100 100 100.00
edn_genbits 67.360s 4979.410us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.470s 22.097us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.880s 251.118us 200 200 100.00
errs 100 100 100.00
edn_err 1.720s 36.671us 100 100 100.00
disable 92 100 92.00
edn_disable 1.260s 134.451us 50 50 100.00
edn_disable_auto_req_mode 7.860s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 6.690s 387.272us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.160s 171.865us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.190s 15.182us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.140s 105.700us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.140s 105.700us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.140s 28.857us 1 1 100.00
edn_csr_rw 1.080s 14.969us 5 5 100.00
edn_csr_aliasing 2.010s 43.445us 1 1 100.00
edn_same_csr_outstanding 1.440s 72.358us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.140s 28.857us 1 1 100.00
edn_csr_rw 1.080s 14.969us 5 5 100.00
edn_csr_aliasing 2.010s 43.445us 1 1 100.00
edn_same_csr_outstanding 1.440s 72.358us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
edn_sec_cm 88.000s 10021.448us 4 5 80.00
edn_tl_intg_err 3.270s 124.372us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.260s 251.763us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.880s 251.118us 200 200 100.00
sec_cm_main_sm_fsm_sparse 4 5 80.00
edn_sec_cm 88.000s 10021.448us 4 5 80.00
sec_cm_ack_sm_fsm_sparse 4 5 80.00
edn_sec_cm 88.000s 10021.448us 4 5 80.00
sec_cm_fifo_ctr_redun 4 5 80.00
edn_sec_cm 88.000s 10021.448us 4 5 80.00
sec_cm_ctr_redun 4 5 80.00
edn_sec_cm 88.000s 10021.448us 4 5 80.00
sec_cm_main_sm_ctr_local_esc 204 205 99.51
edn_alert 1.880s 251.118us 200 200 100.00
edn_sec_cm 88.000s 10021.448us 4 5 80.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.880s 251.118us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.270s 124.372us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 23 30 76.67
edn_stress_all_with_rand_reset 93.850s 20019.520us 23 30 76.67

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
edn_stress_all_with_rand_reset 80746629879221444821888590160018350601966544196593395086462501279919495395383 141
UVM_INFO @ 969513697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 36861551527442923488000990775071901566451895918474454772788974386067042016244 119
UVM_INFO @ 526295052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 10004372722788738941757845471825899712986964806941339795541639980790292561922 168
UVM_INFO @ 1624091043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 49621504527677254450814926403586564961414666040105227865552023923994629494667 281
UVM_INFO @ 3188415560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 70731439282803327810245432970135157993349423670867324259192506725891526884125 350
UVM_INFO @ 3733781468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 89445107416000478403724611505904482797124864548023034978671391170631315866131 198
UVM_INFO @ 1553439930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 6309153265205145838149496441823991005732116050017527591055069094017567301792 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 10473583692581710561247120375608574870157906305500711353483322724364721622479 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 72819583191452937040346816637505996426213045741581226132989819828693810833115 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 31370304144889080617253021586421197644310752395032470132380987681715151484306 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 55254431898687848462476800028006525331998175744744445046018368564845884372717 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 16113616508699935794301513910026297658084874007965162282295215938993855889447 88
UVM_INFO @ 17544857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 110586370511131903314048523008591174185072842300371343135213191166214829645276 88
UVM_INFO @ 34014995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 92130911729120352268633317442573950927945276312646906830628987940480415175883 88
UVM_INFO @ 90292332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_common_vseq.sv:112) [edn_common_vseq] Waiting for EDN endpoint request timeout 1 test run
edn_sec_cm 73210257791521858993529499227296736062743910830201852830718691579123018711050 98
UVM_INFO @ 10021448047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 109297596513945948446499421509437651343725983391347416640037456348660349263345 240
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1074139349 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup