Simulation Results: hmac

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.11 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 18.000s 1623.988us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 154.516us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 24.324us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 9.000s 587.777us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 348.650us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 349.000s 64624.827us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 24.324us 5 5 100.00
hmac_csr_aliasing 3.000s 348.650us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 90.000s 31265.493us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 134.000s 33034.712us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 311.000s 40426.707us 30 30 100.00
hmac_test_sha384_vectors 645.000s 19434.949us 75 75 100.00
hmac_test_sha512_vectors 661.000s 87817.234us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 475.157us 50 50 100.00
hmac_test_hmac384_vectors 23.000s 504.246us 60 60 100.00
hmac_test_hmac512_vectors 32.000s 2192.076us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 43.000s 10513.983us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 425.000s 62023.590us 10 10 100.00
error 10 10 100.00
hmac_error 179.000s 31449.497us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 146.000s 23222.347us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 18.000s 1623.988us 10 10 100.00
hmac_long_msg 90.000s 31265.493us 10 10 100.00
hmac_back_pressure 134.000s 33034.712us 25 25 100.00
hmac_datapath_stress 425.000s 62023.590us 10 10 100.00
hmac_burst_wr 43.000s 10513.983us 50 50 100.00
hmac_stress_all 1094.000s 147818.005us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 18.000s 1623.988us 10 10 100.00
hmac_long_msg 90.000s 31265.493us 10 10 100.00
hmac_back_pressure 134.000s 33034.712us 25 25 100.00
hmac_datapath_stress 425.000s 62023.590us 10 10 100.00
hmac_wipe_secret 146.000s 23222.347us 10 10 100.00
hmac_test_sha256_vectors 311.000s 40426.707us 30 30 100.00
hmac_test_sha384_vectors 645.000s 19434.949us 75 75 100.00
hmac_test_sha512_vectors 661.000s 87817.234us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 475.157us 50 50 100.00
hmac_test_hmac384_vectors 23.000s 504.246us 60 60 100.00
hmac_test_hmac512_vectors 32.000s 2192.076us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 18.000s 1623.988us 10 10 100.00
hmac_long_msg 90.000s 31265.493us 10 10 100.00
hmac_back_pressure 134.000s 33034.712us 25 25 100.00
hmac_datapath_stress 425.000s 62023.590us 10 10 100.00
hmac_burst_wr 43.000s 10513.983us 50 50 100.00
hmac_error 179.000s 31449.497us 10 10 100.00
hmac_wipe_secret 146.000s 23222.347us 10 10 100.00
hmac_test_sha256_vectors 311.000s 40426.707us 30 30 100.00
hmac_test_sha384_vectors 645.000s 19434.949us 75 75 100.00
hmac_test_sha512_vectors 661.000s 87817.234us 75 75 100.00
hmac_test_hmac256_vectors 21.000s 475.157us 50 50 100.00
hmac_test_hmac384_vectors 23.000s 504.246us 60 60 100.00
hmac_test_hmac512_vectors 32.000s 2192.076us 75 75 100.00
hmac_stress_all 1094.000s 147818.005us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1094.000s 147818.005us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 73.053us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 13.475us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 6.000s 257.129us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 6.000s 257.129us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 154.516us 1 1 100.00
hmac_csr_rw 2.000s 24.324us 5 5 100.00
hmac_csr_aliasing 3.000s 348.650us 1 1 100.00
hmac_same_csr_outstanding 4.000s 171.319us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 154.516us 1 1 100.00
hmac_csr_rw 2.000s 24.324us 5 5 100.00
hmac_csr_aliasing 3.000s 348.650us 1 1 100.00
hmac_same_csr_outstanding 4.000s 171.319us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 56.752us 5 5 100.00
hmac_tl_intg_err 6.000s 244.402us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 6.000s 244.402us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 18.000s 1623.988us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 9.000s 146.185us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 787.000s 345127.115us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 23.053us 1 1 100.00