Simulation Results: lc_ctrl/volatile_unlock_disabled

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.20 %
  • code
  • 93.14 %
  • assert
  • 96.97 %
  • func
  • 89.49 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 88.48 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.30%
V2S
98.67%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 7.000s 839.254us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 24.000s 22.510us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 20.000s 20.806us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 24.000s 35.784us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 24.000s 41.564us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 21.000s 23.430us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 20.000s 20.806us 5 5 100.00
lc_ctrl_csr_aliasing 24.000s 41.564us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 5.000s 192.806us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 12.000s 403.088us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 24.000s 13.138us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 98.286us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 22.000s 6867.419us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_ctrl_prog_failure 4.000s 98.286us 20 20 100.00
lc_ctrl_errors 22.000s 6867.419us 20 20 100.00
lc_ctrl_security_escalation 13.000s 527.122us 20 20 100.00
lc_ctrl_jtag_state_failure 42.000s 2278.361us 19 20 95.00
lc_ctrl_jtag_prog_failure 12.000s 464.596us 20 20 100.00
lc_ctrl_jtag_errors 67.000s 4115.711us 20 20 100.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 13.000s 1389.113us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.000s 2508.556us 18 20 90.00
lc_ctrl_jtag_prog_failure 12.000s 464.596us 20 20 100.00
lc_ctrl_jtag_errors 67.000s 4115.711us 20 20 100.00
lc_ctrl_jtag_access 23.000s 1451.560us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 21.000s 4058.447us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 451.995us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.000s 351.789us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 14.000s 5373.359us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 11.000s 3193.890us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 184.647us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 207.166us 10 10 100.00
lc_ctrl_jtag_alert_test 15.000s 21.228us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 10.000s 478.505us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 18.461us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 225.000s 43223.839us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 25.000s 100.938us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 946.345us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 946.345us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 24.000s 22.510us 1 1 100.00
lc_ctrl_csr_rw 20.000s 20.806us 5 5 100.00
lc_ctrl_csr_aliasing 24.000s 41.564us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 52.539us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 24.000s 22.510us 1 1 100.00
lc_ctrl_csr_rw 20.000s 20.806us 5 5 100.00
lc_ctrl_csr_aliasing 24.000s 41.564us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 52.539us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 6.000s 568.359us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 520.754us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 520.754us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 12.000s 403.088us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_ctrl_sec_cm 6.000s 568.359us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_ctrl_sec_cm 6.000s 568.359us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_ctrl_sec_cm 6.000s 568.359us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_ctrl_sec_cm 6.000s 568.359us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_ctrl_sec_cm 6.000s 568.359us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_ctrl_sec_cm 6.000s 568.359us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_ctrl_sec_cm 6.000s 568.359us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 10.000s 384.004us 20 20 100.00
lc_ctrl_sec_cm 6.000s 568.359us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 13.000s 527.122us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 38 40 95.00
lc_ctrl_state_post_trans 5.000s 192.806us 20 20 100.00
lc_ctrl_jtag_state_post_trans 15.000s 2508.556us 18 20 90.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 15.000s 1405.676us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 15.000s 1405.676us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.000s 2207.206us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 3420.713us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 8.000s 3420.713us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
lc_ctrl_stress_all_with_rand_reset 21.000s 2880.038us 2 10 20.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 8 test runs
lc_ctrl_stress_all_with_rand_reset 105982515343723198154988872072845593501993377620745446454617668515075122890338 562
UVM_INFO @ 1306230985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 32030829595291203410401251650077312706070411847960090821818818676276997444441 3936
UVM_INFO @ 4245582049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103097741774981804948280259757348007853004018251803655880984809685802014507886 2061
UVM_INFO @ 6447880586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 89924091484989698115587603839088650192806667168151866029290623979321328883378 192
UVM_INFO @ 719629400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43831853305233773069359358145314076270400655751662544254297886938134667580403 185
UVM_INFO @ 738160833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 79617506020164175439722394172131413744500485842865188042308433568647983772530 1917
UVM_INFO @ 2843382136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 60356771072945302428362938345123845980139248880934972664636895255613399022776 189
UVM_INFO @ 817918399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47321026523413855689872810794348254184797044991920790022410393481172887203958 2916
UVM_INFO @ 46904093014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 3 test runs
lc_ctrl_jtag_state_post_trans 93292916878322332870257043716205980406399008881951353542198631182940375826604 177
UVM_INFO @ 23229781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 62667165011386848411602034264854929025711919964320751382839828659775149346665 178
UVM_INFO @ 393135529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 1742642387940788181912190096354755681128036362454321191734394421352969929837 177
UVM_INFO @ 59288677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---