Simulation Results: lc_ctrl/volatile_unlock_enabled

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.81 %
  • code
  • 94.12 %
  • assert
  • 96.40 %
  • func
  • 87.90 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 88.51 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
98.59%
V2S
99.33%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.000s 586.475us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 22.638us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 18.854us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 71.418us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 43.470us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 92.782us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 18.854us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 43.470us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 526.294us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 10.000s 1358.400us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 21.612us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 306.354us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 13.000s 1684.909us 20 20 100.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_ctrl_prog_failure 4.000s 306.354us 20 20 100.00
lc_ctrl_errors 13.000s 1684.909us 20 20 100.00
lc_ctrl_security_escalation 11.000s 347.546us 20 20 100.00
lc_ctrl_jtag_state_failure 63.000s 16441.555us 19 20 95.00
lc_ctrl_jtag_prog_failure 12.000s 1717.000us 20 20 100.00
lc_ctrl_jtag_errors 74.000s 4537.314us 19 20 95.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 12.000s 630.276us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 4837.048us 19 20 95.00
lc_ctrl_jtag_prog_failure 12.000s 1717.000us 20 20 100.00
lc_ctrl_jtag_errors 74.000s 4537.314us 19 20 95.00
lc_ctrl_jtag_access 25.000s 1561.834us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.000s 2521.042us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 719.260us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 578.864us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 35.000s 9421.157us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 12.000s 1338.186us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 44.639us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 331.137us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 99.067us 10 10 100.00
jtag_priority 9 10 90.00
lc_ctrl_jtag_priority 18.000s 3092.144us 9 10 90.00
lc_ctrl_volatile_unlock 9 10 90.00
lc_ctrl_volatile_unlock_smoke 2.000s 42.070us 9 10 90.00
stress_all 9 10 90.00
lc_ctrl_stress_all 136.000s 19890.497us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 2.000s 79.432us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 123.198us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 123.198us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 22.638us 1 1 100.00
lc_ctrl_csr_rw 2.000s 18.854us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 43.470us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 37.766us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 22.638us 1 1 100.00
lc_ctrl_csr_rw 2.000s 18.854us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 43.470us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 37.766us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 6.000s 290.318us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 119.512us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 119.512us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 10.000s 1358.400us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_ctrl_sec_cm 6.000s 290.318us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_ctrl_sec_cm 6.000s 290.318us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_ctrl_sec_cm 6.000s 290.318us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_ctrl_sec_cm 6.000s 290.318us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_ctrl_sec_cm 6.000s 290.318us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_ctrl_sec_cm 6.000s 290.318us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_ctrl_sec_cm 6.000s 290.318us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 10.000s 2710.189us 20 20 100.00
lc_ctrl_sec_cm 6.000s 290.318us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 11.000s 347.546us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 4.000s 526.294us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 4837.048us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.000s 587.531us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 10.000s 587.531us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.000s 1788.136us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.000s 1850.557us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 10.000s 1850.557us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
lc_ctrl_stress_all_with_rand_reset 54.000s 27344.183us 1 10 10.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 9 test runs
lc_ctrl_stress_all_with_rand_reset 81520104918222217295956042331243782767098412311476696843409834065747848420840 278
UVM_INFO @ 1198665965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 23987541590738002871992334270685193417213232619102611016680940820447324628606 1049
UVM_INFO @ 830865199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68736972310388955820179282315121424195625293954087302255778157409617352277451 2497
UVM_INFO @ 27344182848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 2629011666667972010530688499557198051218668410859566169070153415426724250503 189
UVM_INFO @ 4776431746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 67866612634300347591540716100314760382834582448921154022280560763040885699389 181
UVM_INFO @ 612563131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108233361631757849202640817786985679663824625761622013800195756501341186776876 2887
UVM_INFO @ 1881454077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 34363200402748940065187156510916763885031767896039069857248637566351264077300 172
UVM_INFO @ 3378395909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 81546347462021786790119752079353072305711560868019147709132070035650718608699 702
UVM_INFO @ 2686564526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73578258005031767009964425076803395248353475850990518258867256102803670991713 364
UVM_INFO @ 1983892306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_jtag_errors 23057919957693587244533648359558439160684810750281689545166037055826734932891 1637
UVM_INFO @ 2818583368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 94558803128943606304960172990268940529577648497700672735355601967410015996753 3431
UVM_INFO @ 15883295098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 2 test runs
lc_ctrl_jtag_state_failure 55664081833842096278748647125854615050979969567920860583955106392554804559132 178
UVM_INFO @ 52615220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 78499347594571019298722325781745436437215619720461934896481904456878525828672 179
UVM_INFO @ 227238082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout lc_ctrl_regs_reg_block.status.transition_successful (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 1 test run
lc_ctrl_volatile_unlock_smoke 112264759512604886298837527995114168922537846063996327561535220952113484064088 158
UVM_INFO @ 121278568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! 1 test run
lc_ctrl_jtag_priority 74709552122034737201329320094268108377376919051219571925674347746742035705989 157
UVM_INFO @ 10025875205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---