Simulation Results

Simulation Results: otbn

03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
91.02 %

code
81.89 %

assert
94.56 %

func
96.61 %

block
97.80 %

line
97.96 %

branch
82.38 %

toggle
82.42 %

FSM
64.79 %

Validation stages

V1		100.00%
V2		98.77%
V2S		96.35%
V3		30.00%
unmapped		100.00%

116/116 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	otbn_smoke	12.000s	86.272us	1	1	100.00
single_binary				100	100	100.00
	otbn_single	111.000s	821.499us	100	100	100.00
csr_hw_reset				1	1	100.00
	otbn_csr_hw_reset	9.000s	48.574us	1	1	100.00
csr_rw				5	5	100.00
	otbn_csr_rw	9.000s	14.825us	5	5	100.00
csr_bit_bash				1	1	100.00
	otbn_csr_bit_bash	11.000s	180.019us	1	1	100.00
csr_aliasing				1	1	100.00
	otbn_csr_aliasing	9.000s	73.005us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	otbn_csr_mem_rw_with_rand_reset	12.000s	68.106us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	otbn_csr_rw	9.000s	14.825us	5	5	100.00
	otbn_csr_aliasing	9.000s	73.005us	1	1	100.00
mem_walk				1	1	100.00
	otbn_mem_walk	113.000s	1486.031us	1	1	100.00
mem_partial_access				1	1	100.00
	otbn_mem_partial_access	34.000s	2628.450us	1	1	100.00

161/163 passed

98.77 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reset_recovery				10	10	100.00
	otbn_reset	42.000s	143.358us	10	10	100.00
multi_error				0	1	0.00
	otbn_multi_err	61.000s	588.511us	0	1	0.00
back_to_back				10	10	100.00
	otbn_multi	206.000s	3754.525us	10	10	100.00
stress_all				10	10	100.00
	otbn_stress_all	152.000s	1557.814us	10	10	100.00
lc_escalation				59	60	98.33
	otbn_escalate	41.000s	121.140us	59	60	98.33
zero_state_err_urnd				5	5	100.00
	otbn_zero_state_err_urnd	8.000s	22.107us	5	5	100.00
sw_errs_fatal_chk				10	10	100.00
	otbn_sw_errs_fatal_chk	127.000s	430.972us	10	10	100.00
alert_test				10	10	100.00
	otbn_alert_test	14.000s	24.699us	10	10	100.00
intr_test				10	10	100.00
	otbn_intr_test	7.000s	25.775us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	otbn_tl_errors	9.000s	158.957us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	otbn_tl_errors	9.000s	158.957us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	otbn_csr_hw_reset	9.000s	48.574us	1	1	100.00
	otbn_csr_rw	9.000s	14.825us	5	5	100.00
	otbn_csr_aliasing	9.000s	73.005us	1	1	100.00
	otbn_same_csr_outstanding	7.000s	22.710us	5	5	100.00
tl_d_partial_access				12	12	100.00
	otbn_csr_hw_reset	9.000s	48.574us	1	1	100.00
	otbn_csr_rw	9.000s	14.825us	5	5	100.00
	otbn_csr_aliasing	9.000s	73.005us	1	1	100.00
	otbn_same_csr_outstanding	7.000s	22.710us	5	5	100.00

V2S

317/329 passed

96.35 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
mem_integrity				25	25	100.00
	otbn_imem_err	12.000s	25.057us	10	10	100.00
	otbn_dmem_err	12.000s	22.590us	15	15	100.00
internal_integrity				15	17	88.24
	otbn_alu_bignum_mod_err	12.000s	57.560us	5	5	100.00
	otbn_controller_ispr_rdata_err	12.000s	23.972us	5	5	100.00
	otbn_mac_bignum_acc_err	10.000s	103.893us	3	5	60.00
	otbn_urnd_err	7.000s	16.056us	2	2	100.00
illegal_bus_access				5	5	100.00
	otbn_illegal_mem_acc	8.000s	14.715us	5	5	100.00
otbn_mem_gnt_acc_err				2	2	100.00
	otbn_mem_gnt_acc_err	8.000s	52.420us	2	2	100.00
otbn_non_sec_partial_wipe				9	10	90.00
	otbn_partial_wipe	8.000s	16.957us	9	10	90.00
tl_intg_err				25	30	83.33
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
	otbn_tl_intg_err	63.000s	363.129us	25	25	100.00
passthru_mem_tl_intg_err				4	5	80.00
	otbn_passthru_mem_tl_intg_err	54.000s	689.944us	4	5	80.00
prim_fsm_check				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
prim_count_check				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_mem_scramble				1	1	100.00
	otbn_smoke	12.000s	86.272us	1	1	100.00
sec_cm_data_mem_integrity				15	15	100.00
	otbn_dmem_err	12.000s	22.590us	15	15	100.00
sec_cm_instruction_mem_integrity				10	10	100.00
	otbn_imem_err	12.000s	25.057us	10	10	100.00
sec_cm_bus_integrity				25	25	100.00
	otbn_tl_intg_err	63.000s	363.129us	25	25	100.00
sec_cm_controller_fsm_global_esc				59	60	98.33
	otbn_escalate	41.000s	121.140us	59	60	98.33
sec_cm_controller_fsm_local_esc				35	40	87.50
	otbn_imem_err	12.000s	25.057us	10	10	100.00
	otbn_dmem_err	12.000s	22.590us	15	15	100.00
	otbn_zero_state_err_urnd	8.000s	22.107us	5	5	100.00
	otbn_illegal_mem_acc	8.000s	14.715us	5	5	100.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_controller_fsm_sparse				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_scramble_key_sideload				100	100	100.00
	otbn_single	111.000s	821.499us	100	100	100.00
sec_cm_scramble_ctrl_fsm_local_esc				35	40	87.50
	otbn_imem_err	12.000s	25.057us	10	10	100.00
	otbn_dmem_err	12.000s	22.590us	15	15	100.00
	otbn_zero_state_err_urnd	8.000s	22.107us	5	5	100.00
	otbn_illegal_mem_acc	8.000s	14.715us	5	5	100.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_scramble_ctrl_fsm_sparse				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_start_stop_ctrl_fsm_global_esc				59	60	98.33
	otbn_escalate	41.000s	121.140us	59	60	98.33
sec_cm_start_stop_ctrl_fsm_local_esc				35	40	87.50
	otbn_imem_err	12.000s	25.057us	10	10	100.00
	otbn_dmem_err	12.000s	22.590us	15	15	100.00
	otbn_zero_state_err_urnd	8.000s	22.107us	5	5	100.00
	otbn_illegal_mem_acc	8.000s	14.715us	5	5	100.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_start_stop_ctrl_fsm_sparse				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_data_reg_sw_sca				100	100	100.00
	otbn_single	111.000s	821.499us	100	100	100.00
sec_cm_ctrl_redun				10	12	83.33
	otbn_ctrl_redun	9.000s	15.701us	10	12	83.33
sec_cm_pc_ctrl_flow_redun				5	5	100.00
	otbn_pc_ctrl_flow_redun	12.000s	33.256us	5	5	100.00
sec_cm_rnd_bus_consistency				5	5	100.00
	otbn_rnd_sec_cm	76.000s	190.290us	5	5	100.00
sec_cm_rnd_rng_digest				5	5	100.00
	otbn_rnd_sec_cm	76.000s	190.290us	5	5	100.00
sec_cm_rf_base_data_reg_sw_integrity				10	10	100.00
	otbn_rf_base_intg_err	11.000s	24.207us	10	10	100.00
sec_cm_rf_base_data_reg_sw_glitch_detect				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_stack_wr_ptr_ctr_redun				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_rf_bignum_data_reg_sw_integrity				10	10	100.00
	otbn_rf_bignum_intg_err	94.000s	344.686us	10	10	100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_loop_stack_ctr_redun				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00
sec_cm_loop_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	14.000s	403.809us	5	5	100.00
sec_cm_call_stack_addr_integrity				5	5	100.00
	otbn_stack_addr_integ_chk	14.000s	403.809us	5	5	100.00
sec_cm_start_stop_ctrl_state_consistency				7	7	100.00
	otbn_sec_wipe_err	27.000s	250.081us	7	7	100.00
sec_cm_data_mem_sec_wipe				100	100	100.00
	otbn_single	111.000s	821.499us	100	100	100.00
sec_cm_instruction_mem_sec_wipe				100	100	100.00
	otbn_single	111.000s	821.499us	100	100	100.00
sec_cm_data_reg_sw_sec_wipe				100	100	100.00
	otbn_single	111.000s	821.499us	100	100	100.00
sec_cm_write_mem_integrity				10	10	100.00
	otbn_multi	206.000s	3754.525us	10	10	100.00
sec_cm_ctrl_flow_count				100	100	100.00
	otbn_single	111.000s	821.499us	100	100	100.00
sec_cm_ctrl_flow_sca				100	100	100.00
	otbn_single	111.000s	821.499us	100	100	100.00
sec_cm_data_mem_sw_noaccess				5	5	100.00
	otbn_sw_no_acc	12.000s	41.499us	5	5	100.00
sec_cm_key_sideload				100	100	100.00
	otbn_single	111.000s	821.499us	100	100	100.00
sec_cm_tlul_fifo_ctr_redun				0	5	0.00
	otbn_sec_cm	19.000s	118.304us	0	5	0.00

3/10 passed

30.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				3	10	30.00
	otbn_stress_all_with_rand_reset	463.000s	2730.819us	3	10	30.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	otbn_smoke_vectorized	9.000s	21.704us	1	1	100.00

Error Messages

	Test	seed	line	log context
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed				5 test runs
	otbn_sec_cm	67276268489710383962862799649338249747026405496264933897553503683400361218165	117	UVM_ERROR @ 89492348 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 89492348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sec_cm	98596231430336514885915079147148213925866279162004753984108960293640806867818	119	UVM_ERROR @ 207872653 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 207872653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sec_cm	114698438655339568822738216394675003349041451224765236528797777342264846365587	101	xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 225695388 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed UVM_ERROR @ 225695388 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 225695388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sec_cm	65170217193672653924679850595571199416127662224410123775772648736905458985132	103	UVM_ERROR @ 29383490 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 29383490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_sec_cm	65925601290894877735571866618083247309121917465337243105912778315762681704863	130	UVM_ERROR @ 118304474 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A UVM_INFO @ 118304474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				4 test runs
	otbn_stress_all_with_rand_reset	70420342947469448214462845391176813589693127574188709472309162818739238674659	218	UVM_INFO @ 752006828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	107103157414905434393425827486727955482926236124782808713999737656108448317045	171	UVM_INFO @ 159368473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	9500508469696522108654746988628809457200713865795232940687929952368093410507	173	UVM_INFO @ 4212205605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	24254179506927713099176662366196384315771310812003175657440538756766143767842	179	UVM_INFO @ 134771522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived.				3 test runs
	otbn_multi_err	19834680663542642865149850951391145118616011359112727761842248028619849429493	412	UVM_INFO @ 588510503 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_passthru_mem_tl_intg_err	10354981077925694733952208669116803235926622526106131673825757475604714716990	91	UVM_INFO @ 39143470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_stress_all_with_rand_reset	47689419585489030517260631357015906588600897417710800290576883558780335588929	154	UVM_INFO @ 37042228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error				2 test runs
	otbn_mac_bignum_acc_err	84105029657910909626939111900394074171885432594543411889079954744506195018801	120	UVM_INFO @ 54138127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otbn_ctrl_redun	59225819552661756208074624734974529355687950308665536768568617293398272882619	111	UVM_INFO @ 72176828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_/rtl/otbn_controller.sv,703): Assertion NoStallOnBranch has failed				1 test run
	otbn_ctrl_redun	60416710189749209425425737595234548020414384801108203730972226324237084930526	122	UVM_ERROR @ 14037181 ps: (otbn_controller.sv:703) [ASSERT FAILED] NoStallOnBranch UVM_INFO @ 14037181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				1 test run
	otbn_mac_bignum_acc_err	47798248699520639557046338629127716923277984979964533112705610072643696566611	None	~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program) ~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^ File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize assert bodysize is not None ^^^^^^^^^^^^^^^^^^^^ AssertionError ninja: build stopped: subcommand failed. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset)				1 test run
	otbn_stress_all_with_rand_reset	112587883306174254470489269844700219699938774924671963497822754653029176810448	317	UVM_INFO @ 973440055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset)				1 test run
	otbn_stress_all_with_rand_reset	73860369011513472670706214843449793736529741469112671862813417107991115647887	151	UVM_INFO @ 10982570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [] vs [*]) value for register otbn_reg_block.status				1 test run
	otbn_partial_wipe	29650185968484162968748082369353957065563870027906147730447941961030453164590	116	UVM_INFO @ 15871333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed				1 test run
	otbn_escalate	97840141216214093528960967903311603450404170438270127025183698355909557404458	126	UVM_ERROR @ 20298456 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A UVM_INFO @ 20298456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---