Simulation Results: rom_ctrl/32kb

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.89 %
  • code
  • 94.00 %
  • assert
  • 97.38 %
  • func
  • 99.29 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.66 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
91.53%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 4.000s 139.463us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 212.773us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 4.000s 129.274us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 4.000s 556.025us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 133.187us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 5.000s 179.015us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 4.000s 129.274us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 133.187us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 385.699us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.000s 167.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.000s 1393.550us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 15.000s 750.515us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.000s 363.422us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 5.000s 534.533us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 679.342us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 679.342us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 212.773us 1 1 100.00
rom_ctrl_csr_rw 4.000s 129.274us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 133.187us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 288.675us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 212.773us 1 1 100.00
rom_ctrl_csr_rw 4.000s 129.274us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 133.187us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.000s 288.675us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.000s 3156.746us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 124.000s 959.392us 5 5 100.00
rom_ctrl_tl_intg_err 37.000s 647.720us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 124.000s 959.392us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 124.000s 959.392us 5 5 100.00
sec_cm_checker_ctr_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
sec_cm_checker_ctrl_flow_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
sec_cm_checker_fsm_local_esc 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
sec_cm_compare_ctrl_flow_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
sec_cm_compare_ctr_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 124.000s 959.392us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 124.000s 959.392us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 4.000s 139.463us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 4.000s 139.463us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 4.000s 139.463us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 37.000s 647.720us 25 25 100.00
sec_cm_bus_local_esc 17 22 77.27
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
rom_ctrl_kmac_err_chk 8.000s 363.422us 2 2 100.00
sec_cm_mux_mubi 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
sec_cm_mux_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
sec_cm_ctrl_redun 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 67.000s 47723.904us 15 20 75.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 17.000s 3156.746us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 124.000s 959.392us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 14 20 70.00
rom_ctrl_stress_all_with_rand_reset 92.000s 13806.714us 14 20 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 6 test runs
rom_ctrl_stress_all_with_rand_reset 2342724422420293393328679415523633560179502754083427327479788039051420502265 91
UVM_INFO @ 325142242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 108006060115883558930467165040165517421903889186466062262878223383558069772725 89
UVM_INFO @ 90657571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 48872163152843185468391082509652722688621431855192633600258610235047889398143 89
UVM_INFO @ 544124031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 36604474266126150600217897431724704646761041788374910497792247969198145505217 91
UVM_INFO @ 254562544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 61204144260443515235657598690974147021940718449228723837439913378987099748382 92
UVM_INFO @ 291666568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 52017272184936937816233706504471349847189462241230324744418991795094467696940 90
UVM_INFO @ 149300115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 5 test runs
rom_ctrl_corrupt_sig_fatal_chk 1389295730325128796736304549431163766019790092380896567508144234326318690087 101
UVM_INFO @ 935741733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 22657760550846898367294945137141879715842860220683650136574925562087318506100 95
UVM_INFO @ 2055761857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 52965247820614676090637898564986072225119060730449000696192147105406470598843 87
UVM_INFO @ 3516204951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 62140715335327152354437808895164912651870664797408081900470338294602282451742 100
UVM_INFO @ 6684670055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 93953357651335759197848217182787903722748191970756008722288239962400223628790 89
UVM_INFO @ 1261860396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 88051067270266837837261450699730329788398206258261617192077550809877238052611 88
UVM_INFO @ 1393549595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 52939437550100283964296230927323738279051835331740112147055308016411173366841 88
UVM_INFO @ 128536225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---