Simulation Results: rom_ctrl/64kb

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.82 %
  • code
  • 94.01 %
  • assert
  • 97.38 %
  • func
  • 99.06 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.000s 219.897us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.000s 707.187us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 7.000s 363.378us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 1416.416us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.000s 297.604us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.000s 1753.252us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 7.000s 363.378us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 297.604us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.000s 289.736us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.000s 302.166us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 8.000s 260.309us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 28.000s 8374.884us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 14.000s 391.052us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 8.000s 298.233us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 13.000s 1065.502us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 13.000s 1065.502us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 9.000s 707.187us 1 1 100.00
rom_ctrl_csr_rw 7.000s 363.378us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 297.604us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.000s 551.212us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 9.000s 707.187us 1 1 100.00
rom_ctrl_csr_rw 7.000s 363.378us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 297.604us 1 1 100.00
rom_ctrl_same_csr_outstanding 10.000s 551.212us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.000s 4542.670us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 263.000s 1466.952us 5 5 100.00
rom_ctrl_tl_intg_err 66.000s 953.020us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 263.000s 1466.952us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 263.000s 1466.952us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 263.000s 1466.952us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 263.000s 1466.952us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.000s 219.897us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.000s 219.897us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.000s 219.897us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 66.000s 953.020us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
rom_ctrl_kmac_err_chk 14.000s 391.052us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 110.000s 3993.338us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.000s 4542.670us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 263.000s 1466.952us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 15 20 75.00
rom_ctrl_stress_all_with_rand_reset 91.000s 4914.313us 15 20 75.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 4 test runs
rom_ctrl_stress_all_with_rand_reset 96944444727469513037777894238713793255708690555377356917081026975565599837300 90
UVM_INFO @ 757478535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 71380661917640026581652225974757864806596082622907102051437116668738961348678 92
UVM_INFO @ 1311404341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 43021448771025999244848623420693574444593608753591683780951603241223139245216 90
UVM_INFO @ 1038553573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 93380317456477449895876486009671721390447716629275835783594986072054939332022 90
UVM_INFO @ 717297914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 74278437998685568133669382212802798732081831893132366257125908831134256309325 88
UVM_INFO @ 1030279830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 41895523207143425581106225527002258611210426089672113591252082700352452924150 88
UVM_INFO @ 260309479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 1 test run
rom_ctrl_stress_all_with_rand_reset 65287748718732780614004795448137454052144192703254491397616483954394495864830 89
UVM_INFO @ 171365251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---