Simulation Results

Simulation Results: rv_dm/use_dmi_interface

03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.52 %

code
83.53 %

assert
96.90 %

func
97.12 %

block
94.01 %

line
94.58 %

branch
83.79 %

toggle
75.39 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		45.56%
V2S		98.00%
V3		5.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	61.000s	4484.573us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	41.000s	286.446us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	48.000s	93.339us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	72.000s	35273.192us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	49.000s	336.594us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	46.000s	4669.061us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	55.000s	8963.936us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	102.000s	81864.965us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	86.000s	31566.674us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	40.000s	483.600us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	44.000s	155.240us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	36.000s	794.577us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	41.000s	94.665us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	44.000s	266.405us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	43.000s	498.416us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	45.000s	99.402us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	49.000s	283.282us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	40.000s	483.600us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	42.000s	199.111us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	43.000s	273.283us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	36.000s	794.577us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	47.000s	54.247us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	35.000s	144.571us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	46.000s	226.542us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	55.000s	11706.832us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	60.000s	2095.032us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	46.000s	142.242us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	60.000s	2095.032us	1	1	100.00
	rv_dm_csr_rw	46.000s	226.542us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	43.000s	188.725us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	40.000s	141.405us	1	1	100.00

82/180 passed

45.56 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	61.000s	4484.573us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	36.000s	798.229us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	42.000s	179.166us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	37.000s	203.798us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	45.000s	2469.388us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	72.000s	17914.665us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	48.000s	96.263us	0	20	0.00
bad_sba				0	20	0.00
	rv_dm_bad_sba_tl_access	56.000s	10649.005us	0	20	0.00
sba_autoincrement				5	20	25.00
	rv_dm_autoincr_sba_tl_access	168.000s	83050.401us	5	20	25.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	44.000s	112.309us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	49.000s	2437.706us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	40.000s	424.419us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	42.000s	191.881us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	47.000s	6135.608us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	130.000s	15142.337us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	33.000s	175.397us	1	1	100.00
stress_all				4	20	20.00
	rv_dm_stress_all	10800.000s	0.000us	4	20	20.00
alert_test				10	10	100.00
	rv_dm_alert_test	48.000s	117.579us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	53.000s	581.657us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	53.000s	581.657us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	60.000s	2095.032us	1	1	100.00
	rv_dm_csr_hw_reset	35.000s	144.571us	1	1	100.00
	rv_dm_csr_rw	46.000s	226.542us	5	5	100.00
	rv_dm_same_csr_outstanding	52.000s	571.466us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	60.000s	2095.032us	1	1	100.00
	rv_dm_csr_hw_reset	35.000s	144.571us	1	1	100.00
	rv_dm_csr_rw	46.000s	226.542us	5	5	100.00
	rv_dm_same_csr_outstanding	52.000s	571.466us	5	5	100.00

V2S

49/50 passed

98.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	49.000s	3511.665us	5	5	100.00
	rv_dm_tl_intg_err	60.000s	15158.356us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	60.000s	15158.356us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	49.000s	2437.706us	2	2	100.00
	rv_dm_debug_disabled	51.000s	150.651us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	49.000s	2437.706us	2	2	100.00
	rv_dm_debug_disabled	51.000s	150.651us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	61.000s	4484.573us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				10	10	100.00
	rv_dm_buffered_enable	46.000s	155.099us	10	10	100.00
sec_cm_sba_tl_lc_gate_fsm_sparse				3	4	75.00
	rv_dm_sparse_lc_gate_fsm	49.000s	247.534us	3	4	75.00
sec_cm_mem_tl_lc_gate_fsm_sparse				3	4	75.00
	rv_dm_sparse_lc_gate_fsm	49.000s	247.534us	3	4	75.00
sec_cm_exec_ctrl_mubi				10	10	100.00
	rv_dm_buffered_enable	46.000s	155.099us	10	10	100.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	20	5.00
	rv_dm_stress_all_with_rand_reset	72.000s	5340.695us	1	20	5.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	263.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				39 test runs
	rv_dm_sba_tl_access	2580361135874915239136238120294986358159792576617990833342236580324656699341	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23829
	rv_dm_bad_sba_tl_access	83103490832867989496796879978489222614567587328925254059231535793123680334532	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23828
	rv_dm_sba_tl_access	26921780934247115173290547280254361345385105294955453486687880808637381338591	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23860
	rv_dm_bad_sba_tl_access	76310908137226556317233333414775547389679484951267509447361986139477697287790	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_sba_tl_access	16737331045384305891073995538529035224521662587082423376748412020047722207876	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
	rv_dm_bad_sba_tl_access	92609006766189885994694223024505739961025714007648169346073960342108069399419	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23916
	rv_dm_sba_tl_access	46279386190893640580183699838922564225822583667089083139411561077036646872953	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23785
	rv_dm_bad_sba_tl_access	25324847320824537304642665650071333449469975567123112136450955389705268919596	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23774
	rv_dm_sba_tl_access	114548814249152226561286641437918941385438385872656400399903317026305492176963	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23862
	rv_dm_bad_sba_tl_access	99151869575297389359020028857805475538301354250768595163810649734172252743765	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10069
	rv_dm_autoincr_sba_tl_access	112703119615077574036156429336177850291073246952414728859704013459669624718679	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24197
	rv_dm_sba_tl_access	53118085939564194427437782265875584815834137908514368410275049195489116105269	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23805
	rv_dm_autoincr_sba_tl_access	90022721826189680099773081084302965751575699322124699422434594323323241460273	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24146
	rv_dm_sba_tl_access	16564274797810243559969700203461812303596449698302849429819838667244280862312	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23794
	rv_dm_bad_sba_tl_access	1867400758127249912626206303369217241927854419464870532401198189342908790778	114	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24300
	rv_dm_autoincr_sba_tl_access	89398043071237959881852629805057242837069319547461360248848594458808649089390	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23876
	rv_dm_sba_tl_access	98170758908595218363568250819740696448315641168231655239103717096693471180505	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23821
	rv_dm_sba_tl_access	10492174915277396821951759217998094734286295155430417967009738167906734333678	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23825
	rv_dm_bad_sba_tl_access	24915715971776024651834018791708789594759720962687959966130226477104918827401	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23879
	rv_dm_sba_tl_access	27893171381537487020413574002484616425740096306934083684287852463550881520954	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_bad_sba_tl_access	12822018299190248827464355115610847773842086150285020108429989553771333446147	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24107
	rv_dm_autoincr_sba_tl_access	39315369678235486448659029065037675423184002779312210958413823825095414641173	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23749
	rv_dm_sba_tl_access	37824518032772124789366619694928408026044547281420037864021264400249801740493	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23816
	rv_dm_sba_tl_access	6916199653042263458670002138593346123824176730774461834417557101616068238000	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_sba_tl_access	21420228823281082553399662392701069095383698717799693616452961248737413203815	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23875
	rv_dm_sba_tl_access	8136277840408453286567054886179409336729895065432153044592097633369178973797	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_autoincr_sba_tl_access	19078389522851880395656880243362774405776090907942063965661270572091757401353	141	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24124
	rv_dm_sba_tl_access	108509094063180256288335334797989543155954396959616079283960414517168230933650	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23812
	rv_dm_bad_sba_tl_access	10821231543173572896306427010795582355910624683529100791083715378301414405954	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_sba_tl_access	59130074563057010729795729934466518522317015993020949656715467994284539945651	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23816
	rv_dm_autoincr_sba_tl_access	38645648449875531833332438538884657703530320187809071824349087191309425563496	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24444
	rv_dm_sba_tl_access	6032490951908130122759371779713465623139444927248958507807991436505889190335	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23804
	rv_dm_sba_tl_access	88166472892701390552533426753409667604758922264695686413422466187453500596106	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23906
	rv_dm_autoincr_sba_tl_access	51886187904206358754456338607356243055895918823132451957694329880659558354014	135	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23963
	rv_dm_sba_tl_access	97901614715156935400588578985956979272397323316449533024856055428478493077846	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23805
	rv_dm_bad_sba_tl_access	94865828569420073873001676627583529051277299851147434984085283458060881288603	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23740
	rv_dm_autoincr_sba_tl_access	22130615405971005580767384265976169405778837357962257745328548167074587869361	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_sba_tl_access	56867712464012023914715782865344406454864546389928331269214182928492659128090	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23873
	rv_dm_bad_sba_tl_access	47233701358776790943955063706059270941691236613437486220126181562393035472280	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23897
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				36 test runs
	rv_dm_delayed_resp_sba_tl_access	41574893703721450899871510873617380579717567333714275733927405801329525757941	107	UVM_INFO @ 60199834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	68662500379269544498457630420065419572239673614925017171331810516372005633873	107	UVM_INFO @ 67559430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	2702944149316291646963627293513936083907414993952739308762187859176408807259	107	UVM_INFO @ 507719440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	39121405794385614927389218936089349105112111624877277092263367653786043657177	107	UVM_INFO @ 404171755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	66791326966153760564773205275444605739511291214080737645223769976844324022551	107	UVM_INFO @ 149046956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	2169577250001801446480656020531536744725816097285521677016685865290412994566	107	UVM_INFO @ 1059243703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	32880117651914802861497482093402867608129759877612421764560442946305670027622	107	UVM_INFO @ 83502044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	13967935333141884888170836358552948364829778615450742536830291729818726541661	107	UVM_INFO @ 42975521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	108588566815505083897421377547862538046216456616095478889070408950572094643113	107	UVM_INFO @ 486473493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	45535909227882567795946210358034939410100093726145656639126674250901485275152	107	UVM_INFO @ 52714237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	98444637260425646570680040045829461818240513171725124114195967914137075120960	107	UVM_INFO @ 468496307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	147340130037149187580380308371973242891762918391852794180993698793949650077	107	UVM_INFO @ 385177218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	31764523736466126563558455208047699707931375031133352110384231044515673554790	107	UVM_INFO @ 103285038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	28606658271441821260721956823434469799187470660310649609809610955757838099326	107	UVM_INFO @ 255534525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	115765269120375400175113850850600585185367806118474952477918057217146488417233	107	UVM_INFO @ 40688377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	82601807813654145331727675875187272647355414421084897492315571639632801209227	107	UVM_INFO @ 183965357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	43017685358210063912499112603396235025180026134431294518165076349032955469512	107	UVM_INFO @ 57284917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	249909583379325810275776867421667096746989393085953145405039643465722195063	107	UVM_INFO @ 136792747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	105027238261224628726884850875340353070421068555495318257972258721182917834416	107	UVM_INFO @ 410651566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	36389198617571256501835144231036082179624136439575831779092356753592945198686	107	UVM_INFO @ 92422235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	15598755695916603931062110225373893177863073361937016985083829243243128482487	107	UVM_INFO @ 311958376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	16845588722073762147555867077697412662862906103158762116376512239641027912207	107	UVM_INFO @ 96673458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	18582673882841691645138032860846271138541069634566757342101881293890669273	107	UVM_INFO @ 76717181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	73888607328478486336715935288624135293343977343857321265174503552277062728309	107	UVM_INFO @ 96262849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	57500224277588547009661362735640465024051398928127289582013782466765403445346	107	UVM_INFO @ 381615232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	8922815538933320691224094116571265167715506749933070628751954545978846381788	107	UVM_INFO @ 370957008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	54692375151721077419909274754033472776385514927315996599689284166417042944747	107	UVM_INFO @ 80939859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	42203295454984568146462990703388038809051602998292260778238429166205391709077	107	UVM_INFO @ 2017821290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	75877905015731953961491731336205929332883451868005454424135078264360417376741	107	UVM_INFO @ 32767104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	102826315644458732836883208045077887744350124850451802374598708217765273493116	107	UVM_INFO @ 50228127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	68988986181986655547628370311094969263834032104920088632112994591393697303602	107	UVM_INFO @ 324291325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	51181369670850072739207201670326174581775159947978980875178968802003304224296	107	UVM_INFO @ 62212557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	72855462113119211192258171633438621408174686102460665443265001346659606425993	107	UVM_INFO @ 4142782880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	78665365438982459476936217801305841898375757456837162588853266264022929589458	107	UVM_INFO @ 120041555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	85464074224636313864746670160169100813786433746321406420382989470603664534905	107	UVM_INFO @ 71181577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	112433762972385625195984841459357926403412174059528104887787063480001719667483	107	UVM_INFO @ 1053538298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				15 test runs
	rv_dm_mem_tl_access_resuming	9584335613265278989713870515737968122142269582416737364706194149929791780816	87	UVM_INFO @ 165200914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	113982405451445609220542417663735573340174460780875637877584504245221902500179	88	UVM_INFO @ 444694469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	32842733255473270027483272529897277178700514515414546911677446691605303048262	91	UVM_INFO @ 149447249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	84810760319425279444656958371399109633723946510201660796188514153792423061436	87	UVM_INFO @ 94664557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	25143124721189608846566346566296343582632584506669290071816291232139376226385	91	UVM_INFO @ 1269314297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	48583103405755755638074488304471640757956707511921607028392705179848640601643	89	UVM_INFO @ 4292375882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	69324665972502222533473914724261877737489346998685623978995942238875829532049	94	UVM_INFO @ 4585679779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	87466402493498391617864021733122581735209473923045770292790287431944821967301	90	UVM_INFO @ 1196366002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	55019620686022255008798134608612657542794891683352986283638467966509358580234	93	UVM_INFO @ 439483729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	43262701876522923052034803906820679581772789078242204286457534821928197713378	97	UVM_INFO @ 198161176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	49396236344530166928902934626954007346773405312858654618942114553831563906524	101	UVM_INFO @ 934319046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	22014762232073476792613271713249419041285208662525113582141305443843407772346	100	UVM_INFO @ 5955916562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	28482704498205970037963040580992964959399587798842207442537749430056324645549	90	UVM_INFO @ 1585318403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	35607289153412789765511208118756913075197998127932452608119503534548818655619	104	UVM_INFO @ 653375571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	3820768405831231910546480829247302643610885135820452879375841074857618627831	102	UVM_INFO @ 894940405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				9 test runs
	rv_dm_hart_unavail	112032753685506399693380629481495541731456396091344669776358797396747718264201	87	UVM_INFO @ 191880551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	78611181373172229230911355784900833525306644741189015074522996055893340176082	87	UVM_INFO @ 107694346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	94105108349348851258461699190000044894914189918748600259974705424009666890275	87	UVM_INFO @ 255245279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	44042517582363926048808087513074141726830050917309787752043119523714318206565	87	UVM_INFO @ 260386414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	76609286596495048760734806716392748367317406683478357200186012707952164206840	92	UVM_INFO @ 401134878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	18350948841460604060313472874850580745961432333609200900920821539821315378950	87	UVM_INFO @ 135503821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	38149169802336856828057289202329612146156337515215076697464342363731876197247	97	UVM_INFO @ 225798494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	29209852382288548572129512459958215636236526191209311271332832269031297440795	88	UVM_INFO @ 451797809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	100631532985080627490915945096858936427260237802714609837063260488510258023608	88	UVM_INFO @ 397381144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				9 test runs
	rv_dm_stress_all_with_rand_reset	76340921659037540949450920089565733469098120256665903988145631602124367200211	103	UVM_INFO @ 601413270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	37873211995794371353873358331288743935116275286877293454476294039354950722380	112	UVM_INFO @ 2461493466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	33129883802863541653113736511215191463101505873620447368732015107512526363639	97	UVM_INFO @ 594804560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	100774943172712348775856801620891106138643553358934579153924203433699098026581	99	UVM_INFO @ 656927786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	112409577114236896913393476955079810586706882638245037682473552606632730474808	104	UVM_INFO @ 669635735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	82411293142369077500474705309863309209662488949600340746570312109795668538332	96	UVM_INFO @ 1619595932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	80202973835090730636720786283678661374920508569053375004855961289857478598772	100	UVM_INFO @ 1253000305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	95064103703592586358220636380371228734266655422017342604050066252853896449926	140	UVM_INFO @ 5340694850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	92945460345127101457883832776024176510044754199099037535021962655347953907439	112	UVM_INFO @ 3736157805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				8 test runs
	rv_dm_jtag_dmi_debug_disabled	75886660617160528376530991301406022342141520412701539941596402230489793006391	87	UVM_INFO @ 112309441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	48877277323707095367955231508708596938154573583197505198235403614300221541802	87	UVM_INFO @ 125532995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	97974584864577755683183645615573285844072932971699049591619953029692000741239	92	UVM_INFO @ 323482454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	74827362446898951519451646927615880185929879240088974107577486477248699855292	91	UVM_INFO @ 3212923410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	113458780798900697570931719490070019214640685830344298852477454746721353424776	97	UVM_INFO @ 738171908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	50825049135205375622362956073023389049846285031455636261482963807514977760270	89	UVM_INFO @ 958658257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	108993996610901261749364851149405199708454587442253026652721859580318731507167	88	UVM_INFO @ 681560296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	85521127184920362882545416541483094594746923142566431743404389609219922221294	95	UVM_INFO @ 2162482490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	rv_dm_scanmode	99685861881332531838885416471517960822138588906101545679822322375514034923943	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45556674577711712113242492445578711264577902512388145589710677915930083737078	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	rv_dm_stress_all	20691652514322227587453265344800346660208831215956429236631633490944734292370	None
	rv_dm_stress_all	98620382908742267711372481655951270467173235486200032756985285662508521395483	None
UVM_ERROR (cip_base_vseq.sv:1381) [rv_dm_sparse_lc_gate_fsm_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_fault does not trigger!				1 test run
	rv_dm_sparse_lc_gate_fsm	56909614673313383492872925911589928562993783350782907792072129671183397149966	87	UVM_INFO @ 46842820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---