Simulation Results: rv_timer

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.98 %
  • code
  • 95.85 %
  • assert
  • 98.10 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 89.26 %
Validation stages
V1
100.00%
V2
85.83%
V2S
100.00%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.000s 721.852us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 50.714us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 1.000s 26.618us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 671.225us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 19.381us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 34.044us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 1.000s 26.618us 5 5 100.00
rv_timer_csr_aliasing 2.000s 19.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 2 20 10.00
rv_timer_random_reset 8.000s 7797.397us 2 20 10.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 1892.268us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 649.000s 4250096.523us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 649.000s 4250096.523us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 11.000s 4767.963us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 32.012us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 1.000s 108.348us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 55.712us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 55.712us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 50.714us 1 1 100.00
rv_timer_csr_rw 1.000s 26.618us 5 5 100.00
rv_timer_csr_aliasing 2.000s 19.381us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 70.812us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 50.714us 1 1 100.00
rv_timer_csr_rw 1.000s 26.618us 5 5 100.00
rv_timer_csr_aliasing 2.000s 19.381us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 70.812us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 1.000s 35.394us 5 5 100.00
rv_timer_tl_intg_err 2.000s 79.496us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 79.496us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 10 10.00
rv_timer_min 4.000s 1384.080us 1 10 10.00
max_value 0 10 0.00
rv_timer_max 2.000s 111.998us 0 10 0.00
stress_all_with_rand_reset 13 20 65.00
rv_timer_stress_all_with_rand_reset 60.000s 29148.088us 13 20 65.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 27 test runs
rv_timer_min 23976844194481876492558852508657923873714494757646177209580734399034710267848 84
UVM_INFO @ 192840486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 78699435961269103011192745935012310163253610267488317879897578059151968075346 84
UVM_INFO @ 148320666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 66397516242090497710488113026401109412399259884398856175585180892458768722803 87
UVM_INFO @ 73260132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 21585501009222635799534461583918348560707961235169027620969319407315287960737 84
UVM_INFO @ 731034727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 73108791032079387037440522497842612360954110817040975589676697071661808479667 84
UVM_INFO @ 70634704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 79354878166783161422035346585375332807787673095309013947072729276462241138446 84
UVM_INFO @ 108534227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 50800823511674591719829597633950236368810026178848937743188063829722483892430 84
UVM_INFO @ 590256665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 31517173106517218847492373129334417737713316447442388405080983442334271160654 84
UVM_INFO @ 1384079960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 58262896088020760326456083843475834932177813264485729799426479714615369851580 85
UVM_INFO @ 250301432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 64789767365148613720602123334530857288201897731600101752272232858237443923383 84
UVM_INFO @ 78586082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 104951018026334724951498961649091467052258506358593670980267572792896547731645 84
UVM_INFO @ 100848593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 30450781456707670239071422306127531298260376574324115776715491056832361122865 85
UVM_INFO @ 75350578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 37205861842800105822148533428416621832326227748881279294688230915811660997677 85
UVM_INFO @ 2499548942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 97617087202933625427239206306877202435539627663842905117674300615530791845641 84
UVM_INFO @ 92037922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 19495241197241449154893180452128546364368847213720983262577607815570207492446 84
UVM_INFO @ 455349245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 110450374221891680588759543429635295133242458570093833717253115759118719309054 84
UVM_INFO @ 771208759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 78852920797972763471485484228639460407558315045698340661435891739976522800040 84
UVM_INFO @ 2134918576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 106891473870000873858704329125496683773858643723698875690619022729544103276136 84
UVM_INFO @ 125471488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 54042248886918470379401113583608694962780226294058423943907068297224143068780 84
UVM_INFO @ 65237339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 71477475468914887154767562613214364734267387636490970882681187261844263941117 84
UVM_INFO @ 7797397151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 11565581625598241227452549632136097949618441854734293418295577811300253963650 84
UVM_INFO @ 260482230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 76736251977646209883809108922252492336969064303922824251409524706864136299236 84
UVM_INFO @ 80809331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 94504036763893049657748345872711437670919083061150746903801698741788252634535 84
UVM_INFO @ 165570403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 40031836124118114874001599470001905838665414159557332145105612677938693563423 85
UVM_INFO @ 186877466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 79523141079241694460977778938976239336576455160189677925240289012130115479433 84
UVM_INFO @ 162872980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 744885659690927579808963750344416145067477973866406651009250515641284705773 84
UVM_INFO @ 812253244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 96453731890570638463177142145856650193837915784669230242135660790843269590308 84
UVM_INFO @ 76649356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 52183768862904967995216913132835007550642916695705375282864601278951856718211 84
UVM_INFO @ 44482629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 92555688436179494721968062002319389730947416251241732964683168614457857435511 85
UVM_INFO @ 111998269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 113293842000465806731971308071088888567858663044010150080668025494438392324409 84
UVM_INFO @ 43079333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 114118824937043875440096661973165919280755849618147202493106564130636515027320 84
UVM_INFO @ 48816575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 38350619495376835316998331015445893851962283429899376157774300982873222800422 84
UVM_INFO @ 91552555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 83823661231259895034861342963210910326237631247805231531583678096611730883212 84
UVM_INFO @ 172267761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 8058739580763897292574463418825877726684100544039276291157263994247489806865 85
UVM_INFO @ 90994900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 101777865909444984595267065190261817213889919976499054557971582795333071844551 84
UVM_INFO @ 49217236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 104648265473279254155855823909337019251102711057106214448542545190908920978527 85
UVM_INFO @ 387170788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 5 test runs
rv_timer_stress_all_with_rand_reset 18353436950342799232721994758431341645276597291694411286433313128812237979629 121
UVM_INFO @ 4294145974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 22875095132928654127215133595910845075412256885442919237142890399093186400224 136
UVM_INFO @ 766701298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 84855406371507892893839857825997024067887556483682497828709459414518255140362 517
UVM_INFO @ 21522120732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 63099904633849780764796497490291390477587641255817520672676875090861487187165 429
UVM_INFO @ 11080137922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 91524554365692652571700560019477364694682296875837801538199404653968539239640 126
UVM_INFO @ 633959095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
rv_timer_stress_all_with_rand_reset 84821015982029034487381937046102512216502052811173585408163826401341571606435 104
UVM_INFO @ 570648311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 63009180417280858980028997773343509588571478216829377983798249624510523606572 254
UVM_INFO @ 8025135680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:347) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 61844050470577985733115279991786948730116603614789075052680531260442923013330 84
UVM_INFO @ 85476733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---