Simulation Results: spi_host

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.95 %
  • code
  • 91.30 %
  • assert
  • 96.79 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.90%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 45.000s 1687.891us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 62.529us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 33.077us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 503.313us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 309.405us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 32.374us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 33.077us 5 5 100.00
spi_host_csr_aliasing 1.000s 309.405us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 14.971us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 16.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 24.838us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 26.000s 1414.441us 10 10 100.00
spi_host_error_cmd 2.000s 16.931us 10 10 100.00
spi_host_event 100.000s 14821.243us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 6.000s 138.579us 10 10 100.00
speed 10 10 100.00
spi_host_speed 6.000s 138.579us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 6.000s 138.579us 10 10 100.00
upper_range_clkdiv 4 5 80.00
spi_host_upper_range_clkdiv 363.000s 200000.000us 4 5 80.00
sw_reset 10 10 100.00
spi_host_sw_reset 94.000s 4814.578us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 352.425us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 6.000s 138.579us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 6.000s 138.579us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 45.000s 1687.891us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 45.000s 1687.891us 10 10 100.00
stress_all 9 10 90.00
spi_host_stress_all 36.000s 2943.872us 9 10 90.00
spien 10 10 100.00
spi_host_spien 60.000s 7448.347us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 171.000s 14668.587us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 3.000s 196.048us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 26.000s 1414.441us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 46.588us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 33.432us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 1486.231us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 1486.231us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 62.529us 1 1 100.00
spi_host_csr_rw 2.000s 33.077us 5 5 100.00
spi_host_csr_aliasing 1.000s 309.405us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 70.168us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 1.000s 62.529us 1 1 100.00
spi_host_csr_rw 2.000s 33.077us 5 5 100.00
spi_host_csr_aliasing 1.000s 309.405us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 70.168us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 95.427us 25 25 100.00
spi_host_sec_cm 2.000s 213.046us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 95.427us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
spi_host_upper_range_clkdiv 22353847226965200617237627636819220761246889484347410250862434692453158689457 135
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_stress_all 56702594555970798919448400866758729735626263032080922518451570668797481796009 328
UVM_INFO @ 10372190944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---