Simulation Results: sram_ctrl/main

 
03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.86 %
  • code
  • 95.87 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.17 %
  • line
  • 96.90 %
  • branch
  • 94.34 %
  • toggle
  • 92.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
87.50%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 8.000s 2762.161us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 70.477us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 47.670us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 60.274us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 14.806us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 2336.463us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 47.670us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 14.806us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 256.000s 46306.377us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 139.000s 4808.706us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 48.000s 6569.530us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 261.000s 68461.063us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 254.000s 174941.204us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 78.000s 28585.767us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 82.000s 142871.315us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 37.000s 11701.092us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 6.000s 2709.892us 8 8 100.00
sram_ctrl_partial_access_b2b 310.000s 98492.626us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 2749.860us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 689.677us 0 8 0.00
sram_ctrl_throughput_w_readback 7.000s 3160.294us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 23.000s 2203.777us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 4.000s 346.935us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 635.000s 70241.329us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 34.488us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 2075.683us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 2075.683us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 70.477us 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.670us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 14.806us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.086us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 70.477us 1 1 100.00
sram_ctrl_csr_rw 2.000s 47.670us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 14.806us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 25.086us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 38.000s 7425.624us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 1308.264us 5 5 100.00
sram_ctrl_tl_intg_err 3.000s 373.973us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 1308.264us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 3.000s 373.973us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 23.000s 2203.777us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 23.000s 2203.777us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 47.670us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 37.000s 11701.092us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 37.000s 11701.092us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 37.000s 11701.092us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 82.000s 142871.315us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 7.000s 691.060us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 38.000s 7425.624us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 7.000s 759.542us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 8.000s 2762.161us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 8.000s 2762.161us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 37.000s 11701.092us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 1308.264us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 82.000s 142871.315us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 1308.264us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1308.264us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 8.000s 2762.161us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 1308.264us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 8 87.50
sram_ctrl_stress_all_with_rand_reset 58.000s 11318.751us 7 8 87.50

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 29683744974685120167547296950350192394922776243387273859743263210510821072111 86
UVM_INFO @ 4383895073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 100350538745839278593318308157467832061178405828609464895365429162437855507243 86
UVM_INFO @ 689677352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 24508650611053703300884809368547595902093305979150861428926148462635912627424 86
UVM_INFO @ 670735270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 79567175206621045532261124644883068349902388951605743077236403596816005374987 86
UVM_INFO @ 2639533862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 75705541657545203952222246299422501865591973727581858226705174516294040951777 86
UVM_INFO @ 690058260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 95142051727088874033020891650267107145974616240052046794789357768344786003203 86
UVM_INFO @ 750444963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 32205360468047574315898176048084368573809500206146365250077592388797128310555 86
UVM_INFO @ 2646285310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 66653374702107415427745991872353500825306185015990125356805184481819187434090 86
UVM_INFO @ 2444480335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 95302209456967967710898443927401004623283303174951434964505201582022731697961 86
UVM_INFO @ 1577392718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 54804751583143233534475508111556458788126101323958414751257733509148090157504 86
UVM_INFO @ 2752207722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 81541771859579606942073905513829495435917835039973717103313370853492236494930 86
UVM_INFO @ 670321730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 110599728851784205317927133446792904421772784269815467431157796633956766678461 86
UVM_INFO @ 2748816107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 45688799432959512250023877655550385303944389721453724452403833152229789851032 86
UVM_INFO @ 673235583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 37084552928125267834239720307764391264111037191948214435870627816640996867042 86
UVM_INFO @ 692346738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 99617130893417748395485380838982288673128984334149227470011176891416482369350 86
UVM_INFO @ 2749860165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 23764317716139871162574530090681785258909073823641777444022813291945419758696 86
UVM_INFO @ 3475093735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 102350479123477468460457744179837366721662265671456938763537282739147895654347 86
UVM_INFO @ 2652620652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 92054635423716933251242959938238346758285449320160190995380181842288900768776 86
UVM_INFO @ 2870816848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 30244206880871074265350166297359067074969486765807302220139350047466811046566 86
UVM_INFO @ 707174448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 44202721401832378653153020155723428821889433402765198445904910083767711535910 86
UVM_INFO @ 672065388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 70287733487197986096354160127746283737791930695107898415109697894095802651812 86
UVM_INFO @ 2744407236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 10078266103928088474790318324795607368895518408281401515031490605943333555995 86
UVM_INFO @ 2010716701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 48446135493021541815462161120996912372839611291000349611703468593848157618452 86
UVM_INFO @ 3160293917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 73962269640593459073793494454962895428453978569114403877180686311741517805260 86
UVM_INFO @ 691607206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_stress_all_with_rand_reset 84915993267632887674378664065792475450327726638623515601346152032033668646138 116
UVM_INFO @ 250831009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---