Simulation Results

Simulation Results: uart

03/07/2026 15:00:30 DVSim: v1.49.0 sha: c632d91 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.09 %

code
92.73 %

assert
98.85 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
73.08 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		96.73%
V2S		100.00%
V3		80.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	uart_smoke	25.000s	6206.350us	10	10	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	15.475us	1	1	100.00
csr_rw				5	5	100.00
	uart_csr_rw	2.000s	15.750us	5	5	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.000s	1069.360us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	22.524us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	uart_csr_mem_rw_with_rand_reset	2.000s	52.162us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	uart_csr_rw	2.000s	15.750us	5	5	100.00
	uart_csr_aliasing	1.000s	22.524us	1	1	100.00

384/397 passed

96.73 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				10	10	100.00
	uart_tx_rx	119.000s	74194.178us	10	10	100.00
parity				20	20	100.00
	uart_smoke	25.000s	6206.350us	10	10	100.00
	uart_tx_rx	119.000s	74194.178us	10	10	100.00
parity_error				20	20	100.00
	uart_intr	96.000s	442429.275us	10	10	100.00
	uart_rx_parity_err	248.000s	157714.112us	10	10	100.00
watermark				20	20	100.00
	uart_tx_rx	119.000s	74194.178us	10	10	100.00
	uart_intr	96.000s	442429.275us	10	10	100.00
fifo_full				10	10	100.00
	uart_fifo_full	439.000s	224289.072us	10	10	100.00
fifo_overflow				10	10	100.00
	uart_fifo_overflow	183.000s	115873.396us	10	10	100.00
fifo_reset				199	200	99.50
	uart_fifo_reset	450.000s	155818.044us	199	200	99.50
rx_frame_err				10	10	100.00
	uart_intr	96.000s	442429.275us	10	10	100.00
rx_break_err				10	10	100.00
	uart_intr	96.000s	442429.275us	10	10	100.00
rx_timeout				10	10	100.00
	uart_intr	96.000s	442429.275us	10	10	100.00
perf				10	10	100.00
	uart_perf	286.000s	13187.150us	10	10	100.00
sys_loopback				10	10	100.00
	uart_loopback	11.000s	5118.197us	10	10	100.00
line_loopback				10	10	100.00
	uart_loopback	11.000s	5118.197us	10	10	100.00
rx_noise_filter				2	10	20.00
	uart_noise_filter	86.000s	46607.231us	2	10	20.00
rx_start_bit_filter				10	10	100.00
	uart_rx_start_bit_filter	38.000s	30081.430us	10	10	100.00
tx_overide				10	10	100.00
	uart_tx_ovrd	18.000s	6751.737us	10	10	100.00
rx_oversample				10	10	100.00
	uart_rx_oversample	24.000s	4288.103us	10	10	100.00
long_b2b_transfer				10	10	100.00
	uart_long_xfer_wo_dly	992.000s	173704.891us	10	10	100.00
stress_all				6	10	60.00
	uart_stress_all	2709.000s	382960.895us	6	10	60.00
alert_test				10	10	100.00
	uart_alert_test	2.000s	46.898us	10	10	100.00
intr_test				10	10	100.00
	uart_intr_test	1.000s	11.906us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	uart_tl_errors	3.000s	732.809us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	uart_tl_errors	3.000s	732.809us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	uart_csr_hw_reset	1.000s	15.475us	1	1	100.00
	uart_csr_rw	2.000s	15.750us	5	5	100.00
	uart_csr_aliasing	1.000s	22.524us	1	1	100.00
	uart_same_csr_outstanding	2.000s	73.388us	5	5	100.00
tl_d_partial_access				12	12	100.00
	uart_csr_hw_reset	1.000s	15.475us	1	1	100.00
	uart_csr_rw	2.000s	15.750us	5	5	100.00
	uart_csr_aliasing	1.000s	22.524us	1	1	100.00
	uart_same_csr_outstanding	2.000s	73.388us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	uart_sec_cm	2.000s	66.532us	5	5	100.00
	uart_tl_intg_err	2.000s	280.235us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	uart_tl_intg_err	2.000s	280.235us	25	25	100.00

16/20 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				16	20	80.00
	uart_stress_all_with_rand_reset	69.000s	5212.029us	16	20	80.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				12 test runs
	uart_noise_filter	84576520485881121834241117697459888348589334358232022510277371930787606594361	83	UVM_ERROR @ 19146295 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 135826295 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 135866295 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 135886295 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 175 [0xaf]) reg name: uart_reg_block.rdata
	uart_stress_all	85415903444169925347472641654435663021880145224548474356734145240742948938763	87	UVM_ERROR @ 7979106107 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0 UVM_ERROR @ 7979189441 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 7979606111 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (241 [0xf1] vs 127 [0x7f]) reg name: uart_reg_block.rdata UVM_ERROR @ 8350817414 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	73529880324201029072535079026509148130415798122261522221652382461168770557303	84	UVM_ERROR @ 650431551 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 870321551 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 870321551 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 870321551 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
	uart_stress_all	24148340739716077210751998084556243737201981595120674393517796531615762934119	104	UVM_ERROR @ 69551638417 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 69554878417 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 69732238417 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 69732278417 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	30198971524334309884794117741292093734711748028288779093571009449316989536343	84	UVM_ERROR @ 518039858 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 518769614 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 519269632 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 519877762 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	111133301427734314175705021511273762300866519125623540376836079144940924221140	93	UVM_ERROR @ 46020226103 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 46056338530 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 46063317723 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 46140707386 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
	uart_noise_filter	71175218765624945967777057270044146631714667986213110253997335684783413413413	86	UVM_ERROR @ 7372682417 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 7372880340 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 7481102553 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 7482727605 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all	37986936030508252211346912605759571274696992771143923705838224821854638146230	111	UVM_ERROR @ 78500086557 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 79924145739 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 79924145739 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 81076962768 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
	uart_stress_all	77215312484992818128519138276993635960566417895509085255797709154047724878934	97	UVM_ERROR @ 4718653581 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 4719453581 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 4720013581 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 4720533581 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	106962762520129914757207917985553634714707083174224554142435596701873084905595	84	UVM_ERROR @ 5400742513 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 5400742513 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 5587619008 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 6089081353 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4, clk_pulses: 0
	uart_stress_all_with_rand_reset	95261214685104151481300098159670669392438441841496093378665337528845327558041	87	UVM_ERROR @ 128552434 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 128552434 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 231878138 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/148 UVM_INFO @ 347305786 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/148
	uart_stress_all_with_rand_reset	67100321123148739041417800419153047820559937996895361974071919229228016126912	143	UVM_ERROR @ 2812286219 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 2906754851 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/823 UVM_INFO @ 3148303939 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 5/823 UVM_INFO @ 3228140035 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/823
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				2 test runs
	uart_noise_filter	4212563341148693102503901752584100790469740886222611159321254671506862494895	83	UVM_ERROR @ 44442284 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 44463117 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 46567250 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 46567250 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	24674631995444517178267845300978415785761210144598325931914822946037291439591	87	UVM_ERROR @ 70455563222 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 70455896558 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (182 [0xb6] vs 253 [0xfd]) reg name: uart_reg_block.rdata UVM_ERROR @ 70456354895 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 4, clk_pulses: 0 UVM_ERROR @ 70456438229 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR (uart_scoreboard.sv:379) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *				2 test runs
	uart_stress_all_with_rand_reset	52616659615232495417613736811401037491750465419007805245311185332523357490912	207	UVM_ERROR @ 3971792144 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 3971792144 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 4034044136 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/194 UVM_INFO @ 4072946968 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
	uart_stress_all_with_rand_reset	7197801806799428902817010640101147947941790097311828236957102584880747906540	105	UVM_ERROR @ 4433727084 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 4442518821 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 4442518821 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 4448102199 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR (uart_scoreboard.sv:448) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: TxEmpty				1 test run
	uart_fifo_reset	85451067482534624896274368632261791191211058210194097344125448652833717771499	83	UVM_INFO @ 6958054912 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 1/10 UVM_INFO @ 17467989926 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 2/10 UVM_INFO @ 17977194912 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 3/10 UVM_INFO @ 18194764912 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 4/10