Simulation Results: ac_range_check

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.32 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.67 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
96.23%
V2
98.86%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 48.000s 6006.009us 20 20 100.00
ac_range_check_smoke_racl 18 20 90.00
ac_range_check_smoke_racl 75.000s 11146.766us 18 20 90.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 457.866us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 44.217us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 53.000s 5387.610us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 31.000s 6929.592us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 121.025us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 44.217us 5 5 100.00
ac_range_check_csr_aliasing 31.000s 6929.592us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 144.218us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 56.000s 7514.326us 1 1 100.00
stress_all 9 10 90.00
ac_range_check_stress_all 270.000s 21466.793us 9 10 90.00
alert_test 10 10 100.00
ac_range_check_alert_test 29.000s 43.727us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 22.196us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 6.000s 590.413us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 6.000s 590.413us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 457.866us 1 1 100.00
ac_range_check_csr_rw 3.000s 44.217us 5 5 100.00
ac_range_check_csr_aliasing 31.000s 6929.592us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 287.491us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 457.866us 1 1 100.00
ac_range_check_csr_rw 3.000s 44.217us 5 5 100.00
ac_range_check_csr_aliasing 31.000s 6929.592us 1 1 100.00
ac_range_check_same_csr_outstanding 5.000s 287.491us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 18785.393us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 18785.393us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 18785.393us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 23.000s 18785.393us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 125.000s 18910.408us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 24.437us 5 5 100.00
ac_range_check_tl_intg_err 14.000s 819.404us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 320.000s 6080.248us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 49.000s 8414.213us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 3 test runs
ac_range_check_stress_all 12046838297595216696003786703679285183150695831227955924574396686232082495362 4165
UVM_INFO @ 2496839240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 13717088268862776909943831365253399051284125045172762085321615817786449757093 4248
UVM_INFO @ 11146765811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 17687396501888684885540127770995576636767279954835436622790215033818218586002 4114
UVM_INFO @ 2292269039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---