Simulation Results

Simulation Results: clkmgr

10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
82.60 %

code
79.13 %

assert
93.60 %

func
75.07 %

line
90.78 %

branch
93.10 %

cond
87.70 %

toggle
99.06 %

FSM
25.00 %

Validation stages

V1		65.22%
V2		68.38%
V2S		28.57%
V3		5.00%

15/23 passed

65.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	4.650s	233.928us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.550s	44.552us	1	1	100.00
csr_rw				1	5	20.00
	clkmgr_csr_rw	1.430s	36.851us	1	5	20.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	1.450s	36.841us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	2.110s	74.244us	1	1	100.00
csr_mem_rw_with_rand_reset				2	5	40.00
	clkmgr_csr_mem_rw_with_rand_reset	3.640s	177.465us	2	5	40.00
regwen_csr_and_corresponding_lockable_csr				2	6	33.33
	clkmgr_csr_rw	1.430s	36.851us	1	5	20.00
	clkmgr_csr_aliasing	2.110s	74.244us	1	1	100.00

80/117 passed

68.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.760s	54.045us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	11.070s	678.848us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.450s	40.527us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	4.650s	233.928us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.350s	25.522us	0	10	0.00
frequency_timeout				1	10	10.00
	clkmgr_frequency_timeout	1.670s	55.752us	1	10	10.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.350s	25.522us	0	10	0.00
stress_all				1	10	10.00
	clkmgr_stress_all	4.420s	222.597us	1	10	10.00
alert_test				10	10	100.00
	clkmgr_alert_test	3.960s	257.998us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	26.000s	1727.823us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	26.000s	1727.823us	25	25	100.00
tl_d_outstanding_access				3	12	25.00
	clkmgr_csr_hw_reset	1.550s	44.552us	1	1	100.00
	clkmgr_csr_rw	1.430s	36.851us	1	5	20.00
	clkmgr_csr_aliasing	2.110s	74.244us	1	1	100.00
	clkmgr_same_csr_outstanding	1.480s	35.375us	0	5	0.00
tl_d_partial_access				3	12	25.00
	clkmgr_csr_hw_reset	1.550s	44.552us	1	1	100.00
	clkmgr_csr_rw	1.430s	36.851us	1	5	20.00
	clkmgr_csr_aliasing	2.110s	74.244us	1	1	100.00
	clkmgr_same_csr_outstanding	1.480s	35.375us	0	5	0.00

V2S

30/105 passed

28.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	30	0.00
	clkmgr_sec_cm	130.700s	10104.762us	0	5	0.00
	clkmgr_tl_intg_err	2.790s	131.144us	0	25	0.00
shadow_reg_update_error				18	20	90.00
	clkmgr_shadow_reg_errors	2331.810s	200000.000us	18	20	90.00
shadow_reg_read_clear_staged_value				18	20	90.00
	clkmgr_shadow_reg_errors	2331.810s	200000.000us	18	20	90.00
shadow_reg_storage_error				18	20	90.00
	clkmgr_shadow_reg_errors	2331.810s	200000.000us	18	20	90.00
shadowed_reset_glitch				18	20	90.00
	clkmgr_shadow_reg_errors	2331.810s	200000.000us	18	20	90.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.780s	44.403us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	2.790s	131.144us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.350s	25.522us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				1	10	10.00
	clkmgr_frequency_timeout	1.670s	55.752us	1	10	10.00
sec_cm_meas_config_shadow				18	20	90.00
	clkmgr_shadow_reg_errors	2331.810s	200000.000us	18	20	90.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	2.900s	122.098us	10	10	100.00
sec_cm_jitter_config_mubi				1	5	20.00
	clkmgr_csr_rw	1.430s	36.851us	1	5	20.00
sec_cm_idle_ctr_redun				0	5	0.00
	clkmgr_sec_cm	130.700s	10104.762us	0	5	0.00
sec_cm_meas_config_regwen				1	5	20.00
	clkmgr_csr_rw	1.430s	36.851us	1	5	20.00
sec_cm_clk_ctrl_config_regwen				1	5	20.00
	clkmgr_csr_rw	1.430s	36.851us	1	5	20.00
prim_count_check				0	5	0.00
	clkmgr_sec_cm	130.700s	10104.762us	0	5	0.00

1/20 passed

5.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
regwen				1	10	10.00
	clkmgr_regwen	1.250s	12.722us	1	10	10.00
stress_all_with_rand_reset				0	10	0.00
	clkmgr_stress_all_with_rand_reset	19.530s	625.546us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				30 test runs
	clkmgr_tl_intg_err	39676353035530308481011245757944288710365524862998224760253395567997419957266	93	UVM_INFO @ 11644962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	83544216423933514091965496110406267785167922706480477704563319145581125458748	75	UVM_INFO @ 21450205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	44556044677431478892162394882051682997722601576388472180421046716480853241398	76	UVM_INFO @ 6868032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	2556821036963085445435777972641099967117854942711138050889909219097926180151	90	UVM_INFO @ 12573226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	94151160265908613431492844332547212404758853621322644489300225836474884655178	75	UVM_INFO @ 7617714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	44667498302423879806787221253962929495818141296921560767525356437958232421253	82	UVM_INFO @ 21271691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	20629090759556525275779562550244168465714998987868471189598796920991324604625	98	UVM_INFO @ 19893151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	93231963069770864604474989390236313663446424320488275468369623886716094871185	75	UVM_INFO @ 46675875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	38576714133486942824332547911444429097881891775735712512002986258025074642440	101	UVM_INFO @ 17365356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	15369933537706851899014491720569446745075920542554242422879172593205338657537	75	UVM_INFO @ 2555946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	20607707486341491719257582381569449509935493493267977182818605062011887853552	122	UVM_INFO @ 131143568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	31319355453669845071763503191636680120476652337698114613345797957427655952540	75	UVM_INFO @ 9766425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	78178481940837564763608150808622669967520237998056358339661755973023589885829	86	UVM_INFO @ 7842377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	115080916885647458333088930070109615989702077528441210933381093270243429688769	75	UVM_INFO @ 11846761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	89515033996095111322977444097180600055612730525877932244508574334937472813841	97	UVM_INFO @ 37863428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	76631832793676881928285357788850945309323771854881313163099115797373742013199	75	UVM_INFO @ 20635744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	2503169697126875196476151328874924115381510053132958419041741440824793368181	89	UVM_INFO @ 9579530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	84136376832207005189600751898882700709320020702610547923936839655551539803279	75	UVM_INFO @ 3339213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	81403767819652182726923773084672561016358656586366258006089910695585357312889	118	UVM_INFO @ 28942910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	50668471762420447003382997199553702876694889641968787552445600327653869711902	75	UVM_INFO @ 1535572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	9762053765888917592094371002644493856272928094541704252372028256544119570898	75	UVM_INFO @ 13053108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	106221141085505124297247130912482024331149019827407468994696101220934371772937	75	UVM_INFO @ 5967547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	85014033100081853352935056110582158428267104932259657528473074495417805907793	75	UVM_INFO @ 2125106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	10069736108620878237829659929080628471481804044877128591678708460321256459788	75	UVM_INFO @ 3032289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	105249946934423288477001680170190523117951032225865373148980117601596527478900	108	UVM_INFO @ 42443053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	38832967550698922021780685731501633014300789255202666926815421911351211174320	94	UVM_INFO @ 13120876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50295160383575966201892067154734593255400627750763657563993682964728971176040	82	UVM_INFO @ 8673773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	41387200228292523699629973724939500845254095042894562112335456084185350968563	85	UVM_INFO @ 4416068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	57630608308255141580311134781588717303996381366192051059696344426580369840057	85	UVM_INFO @ 17054787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	25094484752574041770390428488865603024707300067430389533571093637871343116163	119	UVM_INFO @ 63790408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				22 test runs
	clkmgr_frequency	101551537449274985498737000383801359340391909864213137029985067955116503964468	75	UVM_INFO @ 16045236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	36386576197612840925911759511180216138689898631964033574513927046989581374773	77	UVM_INFO @ 86652268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	89148259717621706391559043499242456883446491945055426786507339610586278043991	244	UVM_INFO @ 150061749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	78438075816811200324709505885162223973022362795369752050359047776936616651196	76	UVM_INFO @ 5527625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	79452171150216711682847268779108904638866620399592574160878521078070298799448	75	UVM_INFO @ 7827396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	77425165759682883215376273689538654184087106026437716300451167003170202237024	76	UVM_INFO @ 10642740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	37802310292664825689476316441152148703959848021571023067511754588138499082481	90	UVM_INFO @ 76002577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	90474468096368767273927325929416438071002255092077461625985177610473522647284	76	UVM_INFO @ 17587646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	98463613032891726687137943128484829620896474655920710658080891468412775356906	76	UVM_INFO @ 4927262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	95758147637996042444473778872772572044064999620136569172396614949562371071757	77	UVM_INFO @ 175657776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	64699785316584240372671877941180044945914697607230794864397723950596108765755	76	UVM_INFO @ 222597432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	107457047737820652438216984248521732339789704080069518476115893075495565557092	76	UVM_INFO @ 23739439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	113755832506099531697901634122897705904298933778243718537031411973541943250727	105	UVM_INFO @ 347477327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	114311880490487730775091216406512991959879336614634580997340680471888896761229	77	UVM_INFO @ 21856846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	107448660932801366793643242201099734081402111441290201569398139810883767891548	80	UVM_INFO @ 25522216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	112605697569480340351325547664977994646829242323724802125275703711206415819281	76	UVM_INFO @ 20144339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	38276730602545963787572979287906419542188026047499277016553082685640142453479	76	UVM_INFO @ 6295276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	75634202551509988368502346492992396559929043211645845509602851091800452167635	76	UVM_INFO @ 8002289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	101079965312576512291512599755166565105240449659042088248022470905583687347678	79	UVM_INFO @ 17272420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	22182356462119658820230976567480025906288765528154919608454672023846070336613	76	UVM_INFO @ 16977250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	38105485933415394738299901987294315971422484735054757322370631682694907249606	205	UVM_INFO @ 196521772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	92014077313328036688390540605700452799224727604787040641744838786125848027029	75	UVM_INFO @ 10378407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				22 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	113869766960602357389861387766933533631713710714593461415428873534929755830242	75	UVM_INFO @ 3110312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	111395605747311156878598277630223911756731152576280628480493904267094669269056	75	UVM_INFO @ 2785957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	63206804338734827120040025693624902764998069599105771879533859774826580010831	76	UVM_INFO @ 3508161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	92746840717931957025879571166259831187826003185280069748936587892260719188550	76	UVM_INFO @ 9467163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	27133022883095272673516223358093799929500679553238518481415993480994650497547	75	UVM_INFO @ 44403395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	78467740720950797775855767351504172601437122952735864767715653408268648433893	75	UVM_INFO @ 3550673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	11325257792892266087491330273736755203020152109320674372401630535762536428118	75	UVM_INFO @ 6667005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	91742529646348201806766606997648319076981403910851208877271238622459402238207	85	UVM_INFO @ 5592673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	23059160207554801087139285139589496185953622918908607375469258862334845125739	75	UVM_INFO @ 5459223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	66292162973544054523083016676406648349726609224678860899310185031773053895225	75	UVM_INFO @ 12698969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	37166251498677277146469106739042997885592630538618708915531335946124264212088	75	UVM_INFO @ 34101437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	71295012161794549302840499725370376811954950649306961878032224757361195455584	111	UVM_INFO @ 48474898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	23070601642951151768215930084001989463921662176676390397011012783954217981821	75	UVM_INFO @ 55821833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	25140545006343287578011936224506107182571240812350468325984033142443929189157	117	UVM_INFO @ 32944331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	110505520074146484342407683222950314990473221367897700315617152868241840803786	85	UVM_INFO @ 4754341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	79726581444111789253578528302465064204604837048179107878801144141567795388991	75	UVM_INFO @ 10527818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	74347248961465718841884461828483365482263656559489511966190035307779848513061	75	UVM_INFO @ 33203817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	24322005296168529393077013863739140833548363569696737200668010922704279850207	78	UVM_INFO @ 4880006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	5594687455617512629925049667816260395172731797746859905934229575579492298921	100	UVM_INFO @ 11777998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	12527567563227486404735367213464389425820469965426046423395820090330460823244	75	UVM_INFO @ 23210869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	82391197597937934286876296079440826435238607403731467596970517990300088477963	75	UVM_INFO @ 1907211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	87640295421150436024193350301736547551984624775954146583831174220962732699660	85	UVM_INFO @ 14618545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				16 test runs
	clkmgr_frequency_timeout	31846784242614266236298516023218035217999936116835253659784300110219933364333	78	UVM_INFO @ 2890005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	52747573418347738501340233382195787519234131772022080479284979210399982000214	78	UVM_INFO @ 5852915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	57705930304350369585441680579585955856661952955709308479168081640130668281172	97	UVM_INFO @ 190175157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	73841308171133381146598014427278922607126768378722147399014188234536386352154	78	UVM_INFO @ 3501998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	65594882672820683729827857517878412355054845144435099160360169394543973788842	78	UVM_INFO @ 6372494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	96609587160735698500734066911829606227821949037623009968420735753138988895856	78	UVM_INFO @ 3319919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	1648741641537085852998539820958646509694558811894937006291857478811129508440	79	UVM_INFO @ 3113408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	102909930510303577504022304651439781322934423316465110184179155362674690523287	77	UVM_INFO @ 5261486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	103160655831673329622499167870938815419649242702864159853515061097332328449570	78	UVM_INFO @ 7183977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	13111143577472624938425292447550089642829664379896055691026729961331948454125	79	UVM_INFO @ 31248224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	27291698531169967234857048155700679195370476154574776494625521787062738386911	78	UVM_INFO @ 2743048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	37017562622574618588731544678687773612150475131165488265175855013716745484524	79	UVM_INFO @ 9520565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	97386258050434328657166923460586384950532073203655749129500683214562188926060	78	UVM_INFO @ 8288294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	3598681460071130207631913862470195803342985433534782081890752532004146814257	243	UVM_INFO @ 625546450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	21062931980083745698555430118325516217701177040802134667642904678274385445914	145	UVM_INFO @ 39995698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	99291767119655329806385862333028408792002075029691125448434493431144808816604	78	UVM_INFO @ 3876245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				5 test runs
	clkmgr_sec_cm	40586293816221489725010352372116907622596757714385437544536496541889387671333	151	UVM_INFO @ 10191410355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	66781826621650846043969581030511636295111222974946011546021391619465679800809	117	UVM_INFO @ 10104762100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	21983085621311936858451846160465805211087293080775310719378744504718773933738	119	UVM_INFO @ 10171819671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	17025718858049442105245142733277801322671713038066985615754211049560087273411	104	UVM_INFO @ 10192672978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	16104644945512285585623617213057776886491943048110419212038757055888906885656	93	UVM_INFO @ 10040863141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	18989600125371027073821976898075532851276952318869737648008571345048966833721	75	UVM_INFO @ 29732604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	45902756661302596012452313806837363064319708582615584664270287341256775040521	75	UVM_INFO @ 10320279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	56640125186494412116367982489352539276891596372319492064858927261467559420576	75	UVM_INFO @ 5559097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	95108357026412176750704814083040170384789554342655370520704615499566698256420	75	UVM_INFO @ 4227290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	95560360943692829194444350755860313443768120837468222969505757246815892452879	75	UVM_INFO @ 35374588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				5 test runs
	clkmgr_regwen	62488519021147068979065598984595936521811291102157345880686053675510009802356	74	UVM_INFO @ 2466160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	110762206365881458809091212572383922514641881544644916136448660360192351887527	74	UVM_INFO @ 12722143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	90229315255787806639227327952322688242138755314107170036976598052361725164953	74	UVM_INFO @ 4692521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	73319316879870860726528883177676595830712196912755229294468804610695896462588	74	UVM_INFO @ 2134306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	110129411345251609364250244644134878525618429738345930142733493390986989439585	74	UVM_INFO @ 17536466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				4 test runs
	clkmgr_regwen	18617810356838962168616983425980625998037337251184070113976542310164587405412	74	UVM_INFO @ 2465112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	73280759803326897583245978340597005913797989364248675693514506582104767009533	74	UVM_INFO @ 18857925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	60418849770136753706600296791611655512249175807059092690815899030070540637340	74	UVM_INFO @ 9479383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	64332543552350601524884734425968238748966412689174792822058872752691554191097	74	UVM_INFO @ 7452857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	clkmgr_shadow_reg_errors	78169502978656725226040507073619625970138005048615663960149615602373241837879	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	85278528971572905557226692133760974386498206750767914670357165090987944795705	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	76504527767598635484363847647764627715941206703392814365121305802382582031154	75	UVM_INFO @ 36840736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---