Simulation Results

Simulation Results: csrng

10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.82 %

code
96.20 %

assert
97.16 %

func
91.09 %

block
98.53 %

line
99.54 %

branch
96.38 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.09%
V2S		98.68%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	4.000s	163.952us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	32.000s	39.767us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	32.000s	56.655us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	49.000s	571.212us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	38.000s	355.605us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	32.000s	64.163us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	32.000s	56.655us	5	5	100.00
	csrng_csr_aliasing	38.000s	355.605us	1	1	100.00

1282/1307 passed

98.09 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	60.000s	4741.681us	500	500	100.00
err				500	500	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
cmds				2	25	8.00
	csrng_cmds	124.000s	6967.235us	2	25	8.00
life cycle				2	25	8.00
	csrng_cmds	124.000s	6967.235us	2	25	8.00
stress_all				23	25	92.00
	csrng_stress_all	776.000s	46842.890us	23	25	92.00
intr_test				10	10	100.00
	csrng_intr_test	16.000s	58.461us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	32.000s	48.761us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	11.000s	642.711us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	11.000s	642.711us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	32.000s	39.767us	1	1	100.00
	csrng_csr_rw	32.000s	56.655us	5	5	100.00
	csrng_csr_aliasing	38.000s	355.605us	1	1	100.00
	csrng_same_csr_outstanding	4.000s	201.607us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	32.000s	39.767us	1	1	100.00
	csrng_csr_rw	32.000s	56.655us	5	5	100.00
	csrng_csr_aliasing	38.000s	355.605us	1	1	100.00
	csrng_same_csr_outstanding	4.000s	201.607us	5	5	100.00

V2S

1268/1285 passed

98.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	5.000s	112.284us	5	5	100.00
	csrng_tl_intg_err	15.000s	1311.431us	25	25	100.00
sec_cm_config_regwen				15	30	50.00
	csrng_regwen	3.000s	16.589us	10	25	40.00
	csrng_csr_rw	32.000s	56.655us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	60.000s	4741.681us	500	500	100.00
sec_cm_intersig_mubi				23	25	92.00
	csrng_stress_all	776.000s	46842.890us	23	25	92.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
	csrng_sec_cm	5.000s	112.284us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
	csrng_sec_cm	5.000s	112.284us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
	csrng_sec_cm	5.000s	112.284us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
	csrng_sec_cm	5.000s	112.284us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
	csrng_sec_cm	5.000s	112.284us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	60.000s	4741.681us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
sec_cm_constants_lc_gated				23	25	92.00
	csrng_stress_all	776.000s	46842.890us	23	25	92.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	60.000s	4741.681us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	15.000s	1311.431us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
	csrng_sec_cm	5.000s	112.284us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00
	csrng_sec_cm	5.000s	112.284us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	28.000s	1641.201us	200	200	100.00
	csrng_err	24.000s	36.851us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3601.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				21 test runs
	csrng_cmds	24240799117216333791529207711197466558016089559426783736618288230738591201823	100	UVM_INFO @ 119177864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	64138761850982729749029774517756130769559100090625468338014387548698019142967	100	UVM_INFO @ 87428290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	43765472460450892693022638202497100792604518763369888213772234569477154247740	120	UVM_INFO @ 2492351584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	19901013473513858700445988405473096903971636016570369528512578066571826382429	100	UVM_INFO @ 296906654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	40926471942126394998656949652436604793118408008063635067815464734748879570836	110	UVM_INFO @ 313771676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	23324538147496030690268655222365306252394415105434594975396896613704302674940	100	UVM_INFO @ 205737112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24663489056420619982937880203213026545814926619895032233058413431675530498797	100	UVM_INFO @ 243573404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	66714624954793108157930858286026456816499946272004658771046261709101321002057	110	UVM_INFO @ 253047536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	32765549370828568805949444595549812205578539630521450866710560611367894633993	100	UVM_INFO @ 45946284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	62125524941703604477561864953952081396938896400673027477296295171660749147925	100	UVM_INFO @ 46312151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	27481229766978999994636070198553212981881706829461401561009432774074920517517	100	UVM_INFO @ 41161213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	55676989920731957397467948534090352926841936868062857468667236029410295205321	100	UVM_INFO @ 183485661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	82928334508957112606061723828288644286459454247784815931622436960162678228278	100	UVM_INFO @ 26944846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	80947259744985633680176466665196859207542561406331916666881123653887423043264	100	UVM_INFO @ 105951113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	74447430775306127634188397984394187944420332548792290701865960325524575312537	100	UVM_INFO @ 45595340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	79540057667703989527947579309058803087738181154788765892420874923576228425943	100	UVM_INFO @ 255165682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24056420967117036512957330800235663835983650598701575331383617399358019366391	100	UVM_INFO @ 138677975 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	59355655651594602248663307915616940198805003311681963777934887218585102014103	100	UVM_INFO @ 187306016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	100094166165935847776748853123371583180543149730829229009246038521654220847580	100	UVM_INFO @ 70510187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	12929244417037121991086780618481120035596333054241862211224438935237816615024	100	UVM_INFO @ 50035033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	107750432525167715645567405567762339460441618854749150997081085200327427111644	100	UVM_INFO @ 141663964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				11 test runs
	csrng_regwen	49146991008993454485508549416090675904441831925305605132300437436830247925575	99	UVM_INFO @ 4555202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	49154122998515633621172760073774926006405507412678763126447643937012662398371	99	UVM_INFO @ 2905396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	49166515006251312765853204580006172618088367286506144382356055096774102526860	99	UVM_INFO @ 19006135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	50214292585043738969139464391198625625166918646401342255328042298678323608299	99	UVM_INFO @ 10516442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	57869448589048080356703376302412514824316857908675834031970243263750622451454	99	UVM_INFO @ 5941922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	44568765949956330917289781820621493442740435163392462152990255018212820662442	99	UVM_INFO @ 3493715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	2038400454265082269496870127655368376800105130086032512472128280311067311046	99	UVM_INFO @ 2640836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	75112997267666895386286732777577990150646187611329221773104822158533769286632	99	UVM_INFO @ 2553856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	14988743564279225433981474272726710770516451570519535147872911706547611366065	99	UVM_INFO @ 2579637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	59072441799979561778841759723041304535948116052375464006368651533504649599147	99	UVM_INFO @ 3614170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	2933808594732996594812564911664843282531691150247673564855984263174012762829	99	UVM_INFO @ 13987228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				7 test runs
	csrng_stress_all_with_rand_reset	101837306517258424157540314475472464868295720223753427138001594805536352407011	None
	csrng_stress_all_with_rand_reset	17719545441397555605461821351929152323639886630572583945343776794073885402295	None
	csrng_stress_all_with_rand_reset	69912853990347585366544091503035933426577430208342221601074296262486927490728	None
	csrng_stress_all_with_rand_reset	18644706804188912279110409407668561271761128235810645623463923686482930893102	None
	csrng_stress_all_with_rand_reset	8398054568787676240256142654847795338819022803486531212380314358374677930997	None
	csrng_stress_all_with_rand_reset	105982280004591021147483837545609591778406520448188830455100632020564452632038	None
	csrng_stress_all_with_rand_reset	80293226358734901024393617383861887174914305665928596657479356938366710181390	None
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				4 test runs
	csrng_regwen	66135977004849439737199611438786089728638481544224926539580615628998972265112	99	UVM_INFO @ 1615935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	55253766707681788596742320083397619728481936345466145033944661077690081558450	99	UVM_INFO @ 3637043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	96304224040213752996168658776011233428246845272303341170649701727703770600633	99	UVM_INFO @ 14023983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	99026278225871886950051462675689353253437890301356908283677507202285719950539	99	UVM_INFO @ 27329846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				3 test runs
	csrng_stress_all	34709238184648776476322979036720213781432777027220581937360626046963905386220	113	UVM_INFO @ 256765488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	46922157446638234092109769840855994836856596830795586529429892566539938085951	108	UVM_INFO @ 39862624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	91726378593240382111758695155008246231174262457221583300774386052029705612785	123	UVM_INFO @ 15663791012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				2 test runs
	csrng_stress_all_with_rand_reset	44124128582312765187504749185480920541882754534494348416253674619879167533930	104	UVM_INFO @ 41537297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	35220283205429420289255428080268804287076027179791510765616347708719251076568	177	UVM_INFO @ 8350537070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly				1 test run
	csrng_cmds	95239421825458831448571740107601778835520494751111127453552551017838645249725	108	UVM_INFO @ 30731114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				1 test run
	csrng_cmds	43737134430817855099745305313377893140682982373230801699298876322935471180759	103	UVM_INFO @ 411734833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---