Simulation Results: dma

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.24 %
  • code
  • 90.76 %
  • assert
  • 96.61 %
  • func
  • 80.36 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
93.55%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 9.000s 1563.836us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 8.000s 354.443us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 9.000s 472.125us 50 50 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 1.000s 39.172us 1 1 100.00
csr_rw 5 5 100.00
dma_csr_rw 2.000s 27.029us 5 5 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 7.000s 869.686us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 4.000s 1133.377us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 54.431us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
dma_csr_rw 2.000s 27.029us 5 5 100.00
dma_csr_aliasing 4.000s 1133.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 144.000s 14139.810us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 1017.000s 127605.200us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 346.000s 123801.704us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 346.000s 123801.704us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 1017.000s 127605.200us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1694.000s 151670.794us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 346.000s 123801.704us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 18.000s 1099.754us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 355.000s 37828.756us 3 3 100.00
alert_test 10 10 100.00
dma_alert_test 2.000s 40.292us 10 10 100.00
intr_test 10 10 100.00
dma_intr_test 2.000s 22.224us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
dma_tl_errors 5.000s 1177.193us 25 25 100.00
tl_d_illegal_access 25 25 100.00
dma_tl_errors 5.000s 1177.193us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
dma_csr_hw_reset 1.000s 39.172us 1 1 100.00
dma_csr_rw 2.000s 27.029us 5 5 100.00
dma_csr_aliasing 4.000s 1133.377us 1 1 100.00
dma_same_csr_outstanding 3.000s 233.502us 5 5 100.00
tl_d_partial_access 12 12 100.00
dma_csr_hw_reset 1.000s 39.172us 1 1 100.00
dma_csr_rw 2.000s 27.029us 5 5 100.00
dma_csr_aliasing 4.000s 1133.377us 1 1 100.00
dma_same_csr_outstanding 3.000s 233.502us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 27.000s 938.735us 5 5 100.00
dma_generic_stress 1694.000s 151670.794us 5 5 100.00
dma_handshake_stress 346.000s 123801.704us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 11.000s 316.458us 15 15 100.00
tl_intg_err 30 30 100.00
dma_tl_intg_err 5.000s 243.536us 25 25 100.00
dma_sec_cm 2.000s 13.518us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 29 31 93.55
dma_short_transfer 184.000s 16419.848us 24 25 96.00
dma_longer_transfer 14.000s 1301.215us 5 5 100.00
dma_stress_all_with_rand_reset 16.000s 5256.079us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 66731830171992881256185658957636662296140300213507660216343208070772288728257 108
UVM_INFO @ 5256079230ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ *ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of *ps hit, indicating a probable testbench issue 1 test run
dma_short_transfer 11523451357437441921547760631131286807716218634559515589167170667552904907151 1574
UVM_INFO @ 200000000000ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---