Simulation Results: edn/edn0

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.08 %
  • code
  • 95.26 %
  • assert
  • 98.23 %
  • func
  • 58.74 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.68%
V2S
100.00%
V3
83.33%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 20.886us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 23.059us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 23.569us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.000s 110.500us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 77.441us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 34.968us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 23.569us 5 5 100.00
edn_csr_aliasing 2.000s 77.441us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 8.000s 742.498us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 8.000s 742.498us 100 100 100.00
genbits 100 100 100.00
edn_genbits 8.000s 742.498us 100 100 100.00
interrupts 20 20 100.00
edn_intr 3.000s 41.184us 20 20 100.00
alerts 200 200 100.00
edn_alert 3.000s 30.131us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 122.951us 100 100 100.00
disable 92 100 92.00
edn_disable 2.000s 13.076us 50 50 100.00
edn_disable_auto_req_mode 4.000s 500.000us 42 50 84.00
stress_all 30 30 100.00
edn_stress_all 8.000s 600.313us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 16.642us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 59.514us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.000s 122.273us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.000s 122.273us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 2.000s 23.059us 1 1 100.00
edn_csr_rw 2.000s 23.569us 5 5 100.00
edn_csr_aliasing 2.000s 77.441us 1 1 100.00
edn_same_csr_outstanding 2.000s 22.216us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 2.000s 23.059us 1 1 100.00
edn_csr_rw 2.000s 23.569us 5 5 100.00
edn_csr_aliasing 2.000s 77.441us 1 1 100.00
edn_same_csr_outstanding 2.000s 22.216us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 7.000s 1249.071us 5 5 100.00
edn_tl_intg_err 4.000s 240.244us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 45.613us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 30.131us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.000s 1249.071us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 7.000s 1249.071us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 7.000s 1249.071us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 7.000s 1249.071us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 30.131us 200 200 100.00
edn_sec_cm 7.000s 1249.071us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 30.131us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.000s 240.244us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 25 30 83.33
edn_stress_all_with_rand_reset 134.000s 25563.277us 25 30 83.33

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 61250765698396719865034118252205331893752265716703276824110527397281262755228 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 78282541511180275640401429935714163090820491139189067492363786963723806083807 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 88915224367163568843450154670339344607362478868268501785598018524531165963441 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 35015344143294262810955847946247641067010524403279836913910126009975135065638 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 8629877830296714732791653990041145562916626292598903912279475087334830880842 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 66022802965344848942434891371115043006790684689066838832218354373788982732075 141
UVM_INFO @ 257166350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 75401446616621674437997862411025089715574522935288328044769100196565625981393 161
UVM_INFO @ 581103496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 46491931251462161935152468766360374204788247692695228712997281978605407371774 228
UVM_INFO @ 1692790883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 84932233283910970031891999552041483320685035058420504727344189538303372571024 272
UVM_INFO @ 2898357496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 65656767451559774427091329966103804996810531050109315862125377364673032565273 178
UVM_INFO @ 784463356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 54824173262756817840827746697489514515698045686720624247085580804779711280597 103
UVM_INFO @ 9425954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 87629651251795144720090214110933092524469830836706272721559996609195566708629 103
UVM_INFO @ 34053175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 37326456748862314894114471697104592702999130355319634722529478021789751485097 103
UVM_INFO @ 29176208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---