Simulation Results: edn/edn1

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.60 %
  • code
  • 95.65 %
  • assert
  • 98.70 %
  • func
  • 92.44 %
  • line
  • 98.41 %
  • branch
  • 94.16 %
  • cond
  • 94.08 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
98.52%
V2S
100.00%
V3
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.250s 15.533us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.220s 35.704us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 0.960s 24.537us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.370s 78.995us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.540s 52.679us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.390s 54.417us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 0.960s 24.537us 5 5 100.00
edn_csr_aliasing 1.540s 52.679us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 4.870s 751.777us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 4.870s 751.777us 100 100 100.00
genbits 100 100 100.00
edn_genbits 4.870s 751.777us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.440s 24.002us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.760s 272.117us 200 200 100.00
errs 100 100 100.00
edn_err 1.450s 33.298us 100 100 100.00
disable 91 100 91.00
edn_disable 1.250s 15.449us 50 50 100.00
edn_disable_auto_req_mode 6.620s 500.000us 41 50 82.00
stress_all 30 30 100.00
edn_stress_all 6.580s 383.861us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.220s 16.010us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.150s 12.158us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 4.530s 234.021us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 4.530s 234.021us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.220s 35.704us 1 1 100.00
edn_csr_rw 0.960s 24.537us 5 5 100.00
edn_csr_aliasing 1.540s 52.679us 1 1 100.00
edn_same_csr_outstanding 1.650s 36.261us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.220s 35.704us 1 1 100.00
edn_csr_rw 0.960s 24.537us 5 5 100.00
edn_csr_aliasing 1.540s 52.679us 1 1 100.00
edn_same_csr_outstanding 1.650s 36.261us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 5.510s 756.964us 5 5 100.00
edn_tl_intg_err 6.820s 628.000us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.280s 18.800us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.760s 272.117us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.510s 756.964us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.510s 756.964us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.510s 756.964us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.510s 756.964us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.760s 272.117us 200 200 100.00
edn_sec_cm 5.510s 756.964us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.760s 272.117us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 6.820s 628.000us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 21 30 70.00
edn_stress_all_with_rand_reset 119.620s 22339.435us 21 30 70.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 8 test runs
edn_stress_all_with_rand_reset 90013707250605046932699397508032059726470632249747899467654942075698190256134 205
UVM_INFO @ 1941405764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 85414409550029661399334796945049254765351091745615341444892252826484701644548 169
UVM_INFO @ 1055700977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 8191874442570264735422394884906602358692562981213348137863303477660141202987 178
UVM_INFO @ 1160744145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 49891621216921392632277370109115792405977706654604578681988306993164714815963 151
UVM_INFO @ 718633701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 109103430358918496900312915151017158049558683360505179944895467103209584370010 194
UVM_INFO @ 2213999935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 27197243529544780634311566673333088140006067539392444283367983648253394486303 277
UVM_INFO @ 2967435599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 35328272232523642290138756300225264952346333238725538712543082244914202598400 168
UVM_INFO @ 1064379993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 113077948706771386988285884169569870899741546803355618661071690185644541371154 217
UVM_INFO @ 2303193445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 82966237097220733923767069357416827923014251867723662478302876482481844997837 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 47735663565280694442210275014734268218143252870386016983524590137703191120672 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 104638600832191212513395460788738859122198025570198783199900654891250288079498 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 108949072113296471575952810349698352321992742991849019289252080387004617989364 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 12099594839570434864169478546717742656130849252292865102317526548816623635298 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 4 test runs
edn_disable_auto_req_mode 64118263056303893088650939782628406878924981975349430421286510897497776867605 88
UVM_INFO @ 17195322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 52913161649930994639341728062919544464706663895100728079647964707215380321647 88
UVM_INFO @ 19287322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 8499476296579463544665844304471323061308075896809075926144229857696558014698 88
UVM_INFO @ 28428399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 95771460421627507733103843258861331867239013234719204815884897050243353216037 88
UVM_INFO @ 292107421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 97445409172818154828124848979416702582969717564614384999810052937797645317663 184
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 176474147 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup