Simulation Results: hmac

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.11 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 16.000s 5423.421us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 21.425us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 59.076us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 5.000s 310.030us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 2060.429us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 396.000s 41928.087us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 59.076us 5 5 100.00
hmac_csr_aliasing 6.000s 2060.429us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 118.000s 9562.186us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 116.000s 4666.929us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 334.000s 9311.596us 30 30 100.00
hmac_test_sha384_vectors 651.000s 28465.947us 75 75 100.00
hmac_test_sha512_vectors 702.000s 130818.379us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 1019.644us 50 50 100.00
hmac_test_hmac384_vectors 25.000s 532.319us 60 60 100.00
hmac_test_hmac512_vectors 34.000s 1203.911us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 42.000s 10209.583us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 354.000s 39549.750us 10 10 100.00
error 10 10 100.00
hmac_error 132.000s 52434.120us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 129.000s 13618.004us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 16.000s 5423.421us 10 10 100.00
hmac_long_msg 118.000s 9562.186us 10 10 100.00
hmac_back_pressure 116.000s 4666.929us 25 25 100.00
hmac_datapath_stress 354.000s 39549.750us 10 10 100.00
hmac_burst_wr 42.000s 10209.583us 50 50 100.00
hmac_stress_all 1598.000s 121976.915us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 16.000s 5423.421us 10 10 100.00
hmac_long_msg 118.000s 9562.186us 10 10 100.00
hmac_back_pressure 116.000s 4666.929us 25 25 100.00
hmac_datapath_stress 354.000s 39549.750us 10 10 100.00
hmac_wipe_secret 129.000s 13618.004us 10 10 100.00
hmac_test_sha256_vectors 334.000s 9311.596us 30 30 100.00
hmac_test_sha384_vectors 651.000s 28465.947us 75 75 100.00
hmac_test_sha512_vectors 702.000s 130818.379us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 1019.644us 50 50 100.00
hmac_test_hmac384_vectors 25.000s 532.319us 60 60 100.00
hmac_test_hmac512_vectors 34.000s 1203.911us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 16.000s 5423.421us 10 10 100.00
hmac_long_msg 118.000s 9562.186us 10 10 100.00
hmac_back_pressure 116.000s 4666.929us 25 25 100.00
hmac_datapath_stress 354.000s 39549.750us 10 10 100.00
hmac_burst_wr 42.000s 10209.583us 50 50 100.00
hmac_error 132.000s 52434.120us 10 10 100.00
hmac_wipe_secret 129.000s 13618.004us 10 10 100.00
hmac_test_sha256_vectors 334.000s 9311.596us 30 30 100.00
hmac_test_sha384_vectors 651.000s 28465.947us 75 75 100.00
hmac_test_sha512_vectors 702.000s 130818.379us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 1019.644us 50 50 100.00
hmac_test_hmac384_vectors 25.000s 532.319us 60 60 100.00
hmac_test_hmac512_vectors 34.000s 1203.911us 75 75 100.00
hmac_stress_all 1598.000s 121976.915us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1598.000s 121976.915us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 4.000s 17.502us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 12.525us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 5.000s 384.233us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 5.000s 384.233us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 21.425us 1 1 100.00
hmac_csr_rw 2.000s 59.076us 5 5 100.00
hmac_csr_aliasing 6.000s 2060.429us 1 1 100.00
hmac_same_csr_outstanding 4.000s 229.174us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 21.425us 1 1 100.00
hmac_csr_rw 2.000s 59.076us 5 5 100.00
hmac_csr_aliasing 6.000s 2060.429us 1 1 100.00
hmac_same_csr_outstanding 4.000s 229.174us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 201.456us 5 5 100.00
hmac_tl_intg_err 6.000s 267.072us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 6.000s 267.072us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 16.000s 5423.421us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 9.000s 129.128us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 236.000s 11423.872us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 4.000s 636.100us 1 1 100.00