Simulation Results: keymgr_dpe

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 66.36 %
  • code
  • 83.91 %
  • assert
  • 97.14 %
  • func
  • 18.04 %
  • block
  • 98.09 %
  • line
  • 98.74 %
  • branch
  • 93.62 %
  • toggle
  • 61.74 %
  • FSM
  • 81.54 %
Validation stages
V1
95.65%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 9 10 90.00
keymgr_dpe_smoke 74.000s 26283.808us 9 10 90.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 2.000s 65.913us 1 1 100.00
csr_rw 5 5 100.00
keymgr_dpe_csr_rw 2.000s 42.005us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 5.000s 415.025us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 3.000s 314.492us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 89.984us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_dpe_csr_rw 2.000s 42.005us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 314.492us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
keymgr_dpe_intr_test 2.000s 33.538us 10 10 100.00
alert_test 10 10 100.00
keymgr_dpe_alert_test 2.000s 13.430us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_dpe_tl_errors 5.000s 630.033us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_dpe_tl_errors 5.000s 630.033us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 65.913us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 42.005us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 314.492us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 61.063us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 65.913us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 42.005us 5 5 100.00
keymgr_dpe_csr_aliasing 3.000s 314.492us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 61.063us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
keymgr_dpe_sec_cm 10.000s 1797.989us 5 5 100.00
keymgr_dpe_tl_intg_err 7.000s 335.574us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 131.360us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 131.360us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 131.360us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 131.360us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 10.000s 321.898us 19 20 95.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 10.000s 1797.989us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 10.000s 1797.989us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert recov_operation_err has unexpected timeout error 1 test run
keymgr_dpe_smoke 5519286572701281225385028016420999973930244367840124378385638880468955226117 142
UVM_INFO @ 19421320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1381) [keymgr_dpe_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 91194996597425745676026933955830419518520706589703386545839131691760858070827 85
UVM_INFO @ 140665683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---