Simulation Results: lc_ctrl/volatile_unlock_disabled

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.38 %
  • code
  • 93.18 %
  • assert
  • 96.83 %
  • func
  • 90.13 %
  • block
  • 96.70 %
  • line
  • 97.39 %
  • branch
  • 91.61 %
  • toggle
  • 88.48 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
98.59%
V2S
98.67%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 24.000s 82.181us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 22.811us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 33.663us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 307.517us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 34.979us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 48.317us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 33.663us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 34.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 17.000s 70.573us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1213.612us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 37.135us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 24.000s 174.935us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 15.000s 395.463us 20 20 100.00
security_escalation 136 140 97.14
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_ctrl_prog_failure 24.000s 174.935us 20 20 100.00
lc_ctrl_errors 15.000s 395.463us 20 20 100.00
lc_ctrl_security_escalation 28.000s 472.168us 20 20 100.00
lc_ctrl_jtag_state_failure 60.000s 6774.646us 17 20 85.00
lc_ctrl_jtag_prog_failure 30.000s 1869.534us 19 20 95.00
lc_ctrl_jtag_errors 66.000s 15779.860us 20 20 100.00
jtag_access 207 210 98.57
lc_ctrl_jtag_smoke 27.000s 162.470us 20 20 100.00
lc_ctrl_jtag_state_post_trans 28.000s 1379.429us 18 20 90.00
lc_ctrl_jtag_prog_failure 30.000s 1869.534us 19 20 95.00
lc_ctrl_jtag_errors 66.000s 15779.860us 20 20 100.00
lc_ctrl_jtag_access 21.000s 5544.238us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 30.000s 2584.779us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 6.000s 300.110us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 64.876us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 20.000s 2697.447us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 20.000s 2826.327us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 52.802us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 139.799us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 60.017us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 27.000s 1620.387us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 148.751us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 156.000s 43084.004us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 3.000s 119.083us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 19.000s 1632.176us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 19.000s 1632.176us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 22.811us 1 1 100.00
lc_ctrl_csr_rw 2.000s 33.663us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 34.979us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 51.296us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 22.811us 1 1 100.00
lc_ctrl_csr_rw 2.000s 33.663us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 34.979us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 51.296us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 9.000s 716.435us 5 5 100.00
lc_ctrl_tl_intg_err 15.000s 44.371us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 15.000s 44.371us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1213.612us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_ctrl_sec_cm 9.000s 716.435us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_ctrl_sec_cm 9.000s 716.435us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_ctrl_sec_cm 9.000s 716.435us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_ctrl_sec_cm 9.000s 716.435us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_ctrl_sec_cm 9.000s 716.435us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_ctrl_sec_cm 9.000s 716.435us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_ctrl_sec_cm 9.000s 716.435us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 25.000s 388.001us 20 20 100.00
lc_ctrl_sec_cm 9.000s 716.435us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 28.000s 472.168us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 38 40 95.00
lc_ctrl_state_post_trans 17.000s 70.573us 20 20 100.00
lc_ctrl_jtag_state_post_trans 28.000s 1379.429us 18 20 90.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 510.176us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 11.000s 510.176us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 11.000s 1791.357us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.000s 2180.838us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.000s 2180.838us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 61.000s 15374.418us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 5 test runs
lc_ctrl_jtag_state_failure 105251037544958120487535522718390783537919562013793210437462776686134783996623 178
UVM_INFO @ 134192980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 106346751727574413846380809236615806343950618282427606189281958995880119519799 178
UVM_INFO @ 595434872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 66554975626015929179792004006556666418779336675247299471873197225173990666501 177
UVM_INFO @ 88095445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 101217705409032780803302115970146327617447172126072855531986354195402039037696 179
UVM_INFO @ 90307329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 4888078165519962196874633441092249616017797055738702989767623672281303488190 178
UVM_INFO @ 154569939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 27391092013084254991218868049059113271164060666576119857517367701646361405535 1742
UVM_INFO @ 2938133973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 74743527231064617589169213593120830254387251487869044941551259778320572570842 3699
UVM_INFO @ 3456207052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 109110219786335091560745922575188432172980006778130071665604416833668682713934 500
UVM_INFO @ 1455879739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 63818984088074043780666248803069331452086424504828894179819887254577308789120 794
UVM_INFO @ 2450700956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 2 test runs
lc_ctrl_stress_all_with_rand_reset 38027361231202203413437228120082993688186389621518556529853515026064942962552 2379
UVM_INFO @ 11074518403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90153823344019870813893510167961696693430016221885678043285075015650803739385 3303
UVM_INFO @ 16178073361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 107825275613869149728717101696605851513377742613721523596309441493908035528727 179
UVM_INFO @ 39765525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---