Simulation Results: lc_ctrl/volatile_unlock_enabled

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.70 %
  • code
  • 94.15 %
  • assert
  • 96.83 %
  • func
  • 90.13 %
  • block
  • 97.16 %
  • line
  • 97.69 %
  • branch
  • 92.79 %
  • toggle
  • 88.51 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.53%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 5.000s 1183.088us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 44.780us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 16.449us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 37.119us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 83.830us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 31.546us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 16.449us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 83.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 75.111us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1421.619us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 15.371us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 8.000s 37.657us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 9.000s 3226.348us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_ctrl_prog_failure 8.000s 37.657us 20 20 100.00
lc_ctrl_errors 9.000s 3226.348us 20 20 100.00
lc_ctrl_security_escalation 10.000s 952.334us 20 20 100.00
lc_ctrl_jtag_state_failure 85.000s 10057.761us 19 20 95.00
lc_ctrl_jtag_prog_failure 19.000s 4430.466us 20 20 100.00
lc_ctrl_jtag_errors 63.000s 14509.456us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 15.000s 890.169us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 10954.156us 20 20 100.00
lc_ctrl_jtag_prog_failure 19.000s 4430.466us 20 20 100.00
lc_ctrl_jtag_errors 63.000s 14509.456us 20 20 100.00
lc_ctrl_jtag_access 19.000s 1276.597us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 22.000s 4658.491us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 187.089us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 178.572us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 30.000s 6864.310us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 16.000s 22853.039us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 818.218us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.000s 761.901us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 67.856us 10 10 100.00
jtag_priority 9 10 90.00
lc_ctrl_jtag_priority 15.000s 10006.826us 9 10 90.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 3.000s 49.060us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 290.000s 318018.656us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 2.000s 38.742us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 173.379us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 173.379us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 44.780us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.449us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 83.830us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 318.393us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 44.780us 1 1 100.00
lc_ctrl_csr_rw 2.000s 16.449us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 83.830us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 318.393us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 596.268us 5 5 100.00
lc_ctrl_tl_intg_err 5.000s 245.152us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 5.000s 245.152us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 11.000s 1421.619us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_ctrl_sec_cm 4.000s 596.268us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_ctrl_sec_cm 4.000s 596.268us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_ctrl_sec_cm 4.000s 596.268us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_ctrl_sec_cm 4.000s 596.268us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_ctrl_sec_cm 4.000s 596.268us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_ctrl_sec_cm 4.000s 596.268us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_ctrl_sec_cm 4.000s 596.268us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 11.000s 1352.036us 20 20 100.00
lc_ctrl_sec_cm 4.000s 596.268us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 10.000s 952.334us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 40 40 100.00
lc_ctrl_state_post_trans 4.000s 75.111us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 10954.156us 20 20 100.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.000s 4495.444us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.000s 4495.444us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 12.000s 1949.883us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 810.028us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 810.028us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
lc_ctrl_stress_all_with_rand_reset 101.000s 24162.717us 4 10 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 4 test runs
lc_ctrl_stress_all_with_rand_reset 28691488698112068152733052834265320579318097704980918303178149675422518719219 180
UVM_INFO @ 226642068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 67319174699853613851542346582657958803574484400964319199753902802835639767412 1629
UVM_INFO @ 614495741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18482515304736965097050162623749479650147067232087387105892255425730366239815 2579
UVM_INFO @ 1058433203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47946841558253203828807341211706811554113565149784387676401120030485846704235 1251
UVM_INFO @ 5352000325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_failure 18838526055715815442706283150853121972341592457945663414454330448562800829883 177
UVM_INFO @ 116398785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [lc_ctrl_common_vseq] wait timeout occurred! 1 test run
lc_ctrl_stress_all_with_rand_reset 108000821196496420268012677084363875549238634179285374851424090779949591788865 2467
UVM_INFO @ 24162716521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 111809258410955731344345839396293683055148947866284271221497741391557411685959 2666
UVM_INFO @ 6156282495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! 1 test run
lc_ctrl_jtag_priority 102796474032353747648712468766161070900323010559457010369417362708844115795579 157
UVM_INFO @ 10006825882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---