Simulation Results: rom_ctrl/64kb

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.99 %
  • code
  • 94.01 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 96.76 %
  • line
  • 97.24 %
  • branch
  • 94.09 %
  • toggle
  • 84.70 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
97.18%
V2S
100.00%
V3
85.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 10.000s 301.579us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 7.000s 561.004us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 9.000s 306.613us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.000s 294.576us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.000s 3976.776us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 8.000s 304.061us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 9.000s 306.613us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 3976.776us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.000s 293.629us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.000s 216.961us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 7.000s 787.960us 0 2 0.00
stress_all 20 20 100.00
rom_ctrl_stress_all 34.000s 7957.346us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 11.000s 2018.795us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 11.000s 2096.129us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 10.000s 413.504us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 10.000s 413.504us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.000s 561.004us 1 1 100.00
rom_ctrl_csr_rw 9.000s 306.613us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 3976.776us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.000s 303.694us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 7.000s 561.004us 1 1 100.00
rom_ctrl_csr_rw 9.000s 306.613us 5 5 100.00
rom_ctrl_csr_aliasing 7.000s 3976.776us 1 1 100.00
rom_ctrl_same_csr_outstanding 9.000s 303.694us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.000s 6143.185us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 261.000s 865.199us 5 5 100.00
rom_ctrl_tl_intg_err 69.000s 1126.036us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 261.000s 865.199us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 261.000s 865.199us 5 5 100.00
sec_cm_checker_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
sec_cm_checker_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
sec_cm_checker_fsm_local_esc 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
sec_cm_compare_ctrl_flow_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
sec_cm_compare_ctr_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 261.000s 865.199us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 261.000s 865.199us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 10.000s 301.579us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 10.000s 301.579us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 10.000s 301.579us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 69.000s 1126.036us 25 25 100.00
sec_cm_bus_local_esc 22 22 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
rom_ctrl_kmac_err_chk 11.000s 2018.795us 2 2 100.00
sec_cm_mux_mubi 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
sec_cm_mux_consistency 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
sec_cm_ctrl_redun 20 20 100.00
rom_ctrl_corrupt_sig_fatal_chk 144.000s 7244.391us 20 20 100.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 31.000s 6143.185us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 261.000s 865.199us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 17 20 85.00
rom_ctrl_stress_all_with_rand_reset 146.000s 6842.973us 17 20 85.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 4402485364695403169154767687117743912353296978277081376040149791631752224278 88
UVM_INFO @ 787960019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 95326214385613260726150086730790628642614609590388970317349669127032607372004 88
UVM_INFO @ 3518096329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_scoreboard.sv:235) [scoreboard] Check failed item.d_data[i**+:*] == exp_data[i**+:*] (* [*] vs * [*]) TLUL ROM read data incorrect 2 test runs
rom_ctrl_stress_all_with_rand_reset 114611650167542773168595478474317405445050085809156084124968033369989441061167 96
UVM_INFO @ 532833035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 69727894246593216580111827229382977293646029010283779617230365047610718574398 103
UVM_INFO @ 727394654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal did not trigger max_delay:* 1 test run
rom_ctrl_stress_all_with_rand_reset 53610420562822552004082592959813382511185262224367508218896090864068013617583 91
UVM_INFO @ 686524438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---