Simulation Results

Simulation Results: rv_dm/use_dmi_interface

10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.58 %

code
82.85 %

assert
96.90 %

func
98.00 %

block
93.24 %

line
93.77 %

branch
81.65 %

toggle
75.62 %

FSM
80.36 %

Validation stages

V1		98.46%
V2		45.56%
V2S		96.00%
V3		0.00%
unmapped		0.00%

128/130 passed

98.46 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	46.000s	2978.890us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	46.000s	898.085us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	48.000s	242.584us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	66.000s	13511.797us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	41.000s	539.849us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	59.000s	22004.672us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	47.000s	11293.755us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	149.000s	83664.146us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	154.000s	199896.461us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	37.000s	471.726us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	44.000s	599.641us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	41.000s	428.275us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	47.000s	65.874us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	42.000s	122.770us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	39.000s	327.283us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	38.000s	240.901us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	52.000s	1572.292us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	37.000s	471.726us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	44.000s	113.873us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	38.000s	804.251us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	41.000s	428.275us	2	2	100.00
rom_read_access				2	2	100.00
	rv_dm_rom_read_access	40.000s	71.712us	2	2	100.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	47.000s	103.428us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	42.000s	148.519us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	72.000s	2219.499us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	62.000s	22342.371us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	47.000s	741.187us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	62.000s	22342.371us	1	1	100.00
	rv_dm_csr_rw	42.000s	148.519us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	34.000s	139.744us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	44.000s	60.798us	1	1	100.00

82/180 passed

45.56 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	46.000s	2978.890us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	38.000s	318.257us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	41.000s	275.627us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	42.000s	562.560us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	45.000s	2031.572us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	60.000s	13820.455us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	49.000s	2322.050us	0	20	0.00
bad_sba				1	20	5.00
	rv_dm_bad_sba_tl_access	66.000s	13819.911us	1	20	5.00
sba_autoincrement				7	20	35.00
	rv_dm_autoincr_sba_tl_access	124.000s	42136.050us	7	20	35.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	43.000s	450.183us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	41.000s	5059.904us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	45.000s	295.267us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	46.000s	132.771us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	42.000s	8975.151us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	82.000s	15351.920us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	41.000s	146.046us	1	1	100.00
stress_all				1	20	5.00
	rv_dm_stress_all	10801.000s	0.000us	1	20	5.00
alert_test				10	10	100.00
	rv_dm_alert_test	52.000s	39.285us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	47.000s	761.064us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	47.000s	761.064us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	62.000s	22342.371us	1	1	100.00
	rv_dm_csr_hw_reset	47.000s	103.428us	1	1	100.00
	rv_dm_csr_rw	42.000s	148.519us	5	5	100.00
	rv_dm_same_csr_outstanding	46.000s	670.416us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	62.000s	22342.371us	1	1	100.00
	rv_dm_csr_hw_reset	47.000s	103.428us	1	1	100.00
	rv_dm_csr_rw	42.000s	148.519us	5	5	100.00
	rv_dm_same_csr_outstanding	46.000s	670.416us	5	5	100.00

V2S

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	rv_dm_sec_cm	46.000s	287.259us	5	5	100.00
	rv_dm_tl_intg_err	56.000s	8849.691us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	rv_dm_tl_intg_err	56.000s	8849.691us	25	25	100.00
sec_cm_lc_hw_debug_en_intersig_mubi				3	4	75.00
	rv_dm_sba_debug_disabled	41.000s	5059.904us	2	2	100.00
	rv_dm_debug_disabled	39.000s	49.440us	1	2	50.00
sec_cm_lc_dft_en_intersig_mubi				3	4	75.00
	rv_dm_sba_debug_disabled	41.000s	5059.904us	2	2	100.00
	rv_dm_debug_disabled	39.000s	49.440us	1	2	50.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	46.000s	2978.890us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				9	10	90.00
	rv_dm_buffered_enable	46.000s	135.778us	9	10	90.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	42.000s	74.908us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	42.000s	74.908us	4	4	100.00
sec_cm_exec_ctrl_mubi				9	10	90.00
	rv_dm_buffered_enable	46.000s	135.778us	9	10	90.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	20	0.00
	rv_dm_stress_all_with_rand_reset	81.000s	2285.237us	0	20	0.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	44.000s	0.624us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:414) [scoreboard] sba_tl_access_q item uncompared:				40 test runs
	rv_dm_sba_tl_access	40353149660552452234581533279982109288459096373293195750122901333562357624706	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23865
	rv_dm_bad_sba_tl_access	12033080034417870395692139015811157535169349680812753913284436341697963320778	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23875
	rv_dm_autoincr_sba_tl_access	113417715969111135896044316851140390915467272539544662557831647883809872356494	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_sba_tl_access	26510195308189092567834115822001662655416605518402347609751118377047198918640	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23718
	rv_dm_bad_sba_tl_access	95461390326518034347181779986907334548758001005592704836739782928939288637716	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23771
	rv_dm_sba_tl_access	48831766658451485032821870559259773179766832091126771254257218572794037161411	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_bad_sba_tl_access	58536403586853765409797652972997898619261775395111605512065656288615156165728	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_sba_tl_access	41312089394053289181588241087263693665172531293043694095709342772399821953185	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_sba_tl_access	29022642244536983194732207441231354307039886041617390679976193337966713750218	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_bad_sba_tl_access	110036548879048456620153314201626444740705639432437495321353011391205319256985	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23732
	rv_dm_autoincr_sba_tl_access	5843095590921484824136755294068097684537740774928118208114594518940051207310	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23821
	rv_dm_sba_tl_access	9090872697129348503864943530261052131131382478904694449955409117103282114926	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23885
	rv_dm_bad_sba_tl_access	26797418530647345911634947204252352685121775036264667178334169395601873553596	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23871
	rv_dm_autoincr_sba_tl_access	43170321432705560416324631437017036134533857778773405505059711054298388390304	174	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24074
	rv_dm_sba_tl_access	56063119627279916089529425500069380492764433123869421463336372715722650934953	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10310
	rv_dm_sba_tl_access	98530759347041346976619907965365890570240469428545805438730798939001725640011	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23863
	rv_dm_sba_tl_access	6417539878762067696647538820438418716365854914298943184295043148669800552465	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23870
	rv_dm_bad_sba_tl_access	39242615571644776559186598642023577552958345712310436458607101350277329093705	123	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24093
	rv_dm_sba_tl_access	74595802412227430213951705885998503313823939122390920454253948259089895122526	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23881
	rv_dm_bad_sba_tl_access	50530324312225750724965902958893091615711373984865991535488266979734645985578	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23814
	rv_dm_sba_tl_access	99459815683383212315055127907416192150096356035290986320903498036322869488866	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23807
	rv_dm_sba_tl_access	30854693219607547729326840890257700919887137856069157615410367650775942509982	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23872
	rv_dm_bad_sba_tl_access	94563807350723050616171348615290316880639862079386377149162670076878923712944	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23753
	rv_dm_sba_tl_access	78191333015725691216115340815496287445327773253527436424139427118174249925004	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23808
	rv_dm_bad_sba_tl_access	22355179644601288011494903147612524348030430245965634197983746116271101113334	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23738
	rv_dm_autoincr_sba_tl_access	66180520528619237236368074361089280743548040416793123456054039182979074022646	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23811
	rv_dm_sba_tl_access	66619623329154140246679024015026209504057168323642311801136380763081049117364	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23804
	rv_dm_bad_sba_tl_access	99685602145869631269604943210753781501807945477037177555444839888273166157736	105	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23941
	rv_dm_autoincr_sba_tl_access	44706347354090568164180967274129243763600297273360655949897745741473912488911	144	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23987
	rv_dm_sba_tl_access	95578826735156050674916948157982369383723790415833921135109931327658057751040	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23806
	rv_dm_delayed_resp_sba_tl_access	102075173114963978439269933242068683134769872163179797576673652068645802443437	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23865
	rv_dm_bad_sba_tl_access	74408280666909196776799703499579589787759079351167660050576943434776006623544	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23981
	rv_dm_sba_tl_access	44567369459937568472245271872909835459371925321458994308088575132998094674393	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23869
	rv_dm_bad_sba_tl_access	110250376483067911681379069472888605533570345062937940173594089572446857208400	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24061
	rv_dm_sba_tl_access	90182326874524968398448448221495111718189153021734103219510835944282290358669	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23828
	rv_dm_delayed_resp_sba_tl_access	50299653036249254613883803445476609895907503509002201420926090383299259569586	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23853
	rv_dm_sba_tl_access	23592218824278618866333528190365979777798145032535078750630149873177979925328	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23812
	rv_dm_sba_tl_access	81187475078802357321331629490382568051483243860497874952159286430002309317123	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23868
	rv_dm_autoincr_sba_tl_access	54955433638330062730721607108391994750356065546783558847800086786639571400005	156	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23842
	rv_dm_sba_tl_access	45790063644990870695579969631284526197455791594973562963235346312029941442086	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23873
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				32 test runs
	rv_dm_delayed_resp_sba_tl_access	85721326810655084523264225173937117457034952418314011114696914131875151070484	107	UVM_INFO @ 382203082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	31325650854076693712036971982865749438419539922685003093787789538998395990354	107	UVM_INFO @ 91397759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	20214112588714848633267723956945655141250004284072223170000069980853572945851	107	UVM_INFO @ 411592677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	97495348335782089277755128829960052014583683483485288186334852061364725887789	107	UVM_INFO @ 55090156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	113724717886175924517762296813287937687206010664631825065806907000177284756219	107	UVM_INFO @ 213423576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	102468339864901386245517172106832523109880494108405943316304664451669234977473	107	UVM_INFO @ 178840803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	25962118835796482124126621639486370477587098756556607420847805292407969699153	107	UVM_INFO @ 299925774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	88047756557510912678060703115382545326581957186359833987598079945629472932813	107	UVM_INFO @ 140950405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	55587562501888017926879550683154165004663907114235114233647372551858656035364	107	UVM_INFO @ 470822907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	37189144958425481740157514550269369586234129564817334375887612884097827686667	107	UVM_INFO @ 164445482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	65732755278453880679835483654767519113967357339106234895650066186351768934838	107	UVM_INFO @ 197917124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	79427209839578948806950781527577790857074417556780561382984783504576296491448	107	UVM_INFO @ 567500411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	16218479053912375548344869850688192454264792066443626174030003363292443610600	107	UVM_INFO @ 345290721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	2844333315552674822016268007973087611066500350153445723807833629140602033006	107	UVM_INFO @ 94604828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	107243768123303872735486855071698055989364939628847221853288874182309513849939	107	UVM_INFO @ 286320389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	16697880685592738255666720438607799306812844487479320027248234304830487176928	107	UVM_INFO @ 94390854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	103475666619588137596000640677118211076916967867175080304164038614939465418202	107	UVM_INFO @ 420405222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	29105415148911033577999225161911596317691528389544328375319158799191616540551	107	UVM_INFO @ 212601040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	102823463088239168374456729944336454286647430036045537614613033109408137376767	107	UVM_INFO @ 258421668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	101697651594682928348476116899562949450060813960141970769996594253352977416953	107	UVM_INFO @ 66101050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	67053959713926977851535148638803966355653547906203474123697564846881267547486	107	UVM_INFO @ 266646970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	27215125388791284805285189259101400326451025452369715086561242584808548598214	107	UVM_INFO @ 130206371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	67671058913858562869212428771156263335993227345010091694192056948754116137057	107	UVM_INFO @ 352518457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	76534312202476614678504993482068202522213926128316313061404896149294850195920	107	UVM_INFO @ 328801208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	105058791635332683027443846192150491006362309711470932544746685386112062289322	107	UVM_INFO @ 265629783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	25687843010164908437230929902366448562317795977681442110190748657057910637433	107	UVM_INFO @ 428079955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	29178554775443546812909050393092675576911235122015961089109803714259158400248	107	UVM_INFO @ 712979650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	41836691725366081758697008842579381313622921698460851952278206270246511093880	107	UVM_INFO @ 134253840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	89324616187733732853322934142579261312927458478065933771686306481135670194410	107	UVM_INFO @ 71109586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	65293911386473734225585905133121924521424580799424023850867485448153635512948	107	UVM_INFO @ 253181896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	7168617616899372275820424468851303426832785999566425617011097387051921306561	107	UVM_INFO @ 91817419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	110874218435939054273270978293343339930705331242669623462537120605379878978803	107	UVM_INFO @ 261840956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				18 test runs
	rv_dm_hart_unavail	60215592398351235201151304445711509194634387795526184887586866311799030671852	87	UVM_INFO @ 29809921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	17511477981787858303539103392188994292577792959462352261790080806661622739100	92	UVM_INFO @ 1248803305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	27264630383132729537476090583716002748686662438396194982834314848302260639615	87	UVM_INFO @ 78183566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	109293428589452554656522324669843633233106849602117312312952222173625624883996	97	UVM_INFO @ 217890767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	7920858763548221185003335697995768499031162224785888767260171915973478231571	87	UVM_INFO @ 365577417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	110614146994225880661560648247113850347520340232773882399493607293389837657207	114	UVM_INFO @ 1946683771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	83536719436301770449975363080393119644127725138125097469905975600245533447098	87	UVM_INFO @ 132771161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	14857545014982803908282895589343799052507841747295538459843012124676327546276	87	UVM_INFO @ 73743692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	9035039409408260264701082078204349076276588868495107720328050990989226715362	100	UVM_INFO @ 2912905037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	99596922957160414967848708993390394266201656589015929345009813682985839643818	89	UVM_INFO @ 260058996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	25610849846086285448784243008524611474920316005382910123011938715469092582208	99	UVM_INFO @ 1638251685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	88621776893661653896668808127109122524477472538620424897043993224867081827306	91	UVM_INFO @ 232825915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	84604647041129076199149736437236395435396412227177833009735894392087872819664	90	UVM_INFO @ 3090643947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	2253843419803057038706682325568958223111824751553352978781657263302348712127	117	UVM_INFO @ 7462377906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	103037085070069374261641595139003838826804261221601923710670065745746440118082	89	UVM_INFO @ 380947471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	45590057859267529625941627795051843078397745579153278145046747259357527323052	164	UVM_INFO @ 2285237384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	109298696242323123879732967629585050610320671033134132266169733118135350156563	90	UVM_INFO @ 1201969403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	75371612614918112834360944574031327290949425931232282007021827860294315826579	89	UVM_INFO @ 496425299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				9 test runs
	rv_dm_mem_tl_access_resuming	65276321304227000862565784200621472605849791116607564109898593383995786070471	87	UVM_INFO @ 163043081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	50419419256798839621488676141388173001454700941888786201304630945427561515545	87	UVM_INFO @ 65873840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	49397517383819849552736317138827851031272074171319932946414769536848808510159	92	UVM_INFO @ 109142171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	3442887006843869416905353846994360631536094552263817194062294284280030001041	98	UVM_INFO @ 846979356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	4487118023985625535364739710759552158747934470654137651576689236244152184577	92	UVM_INFO @ 5339170866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	100624718527060016065345892196250046515816911464319747552125179072592435391126	138	UVM_INFO @ 1725231562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	92136449190100952447008003131905375304537756702547613046346223284691231977043	103	UVM_INFO @ 226668404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	111558459290449856443298045035331144784930337043403663785057448709678317136647	92	UVM_INFO @ 376546032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	82910221805585507505069265046645816959171750258533532737642367225582855005646	123	UVM_INFO @ 985472078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				7 test runs
	rv_dm_jtag_dmi_debug_disabled	20743652279257935017799402736123778439986584356607563708645245875545015641642	87	UVM_INFO @ 204764425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	9622767735757859459868368665390638815905989946490930412727774921759183800502	87	UVM_INFO @ 450182917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	54320805866605722303344921989863504584041733016093346486266343612249324437040	95	UVM_INFO @ 324576793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	54045694936481458955419395043347898209507360742121816923154401318911659633349	98	UVM_INFO @ 405484707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	112965723187611666636853896934363470065287010203198655260363478311218884431466	88	UVM_INFO @ 534072707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	98933476395760151377784715474811081427998655202463061865285293186492839820076	95	UVM_INFO @ 756903007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	15091859990350657824978848760953975121634093438555760582407684910483716175366	90	UVM_INFO @ 2336589035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				6 test runs
	rv_dm_stress_all	62823853189117765340137776772737961030890131504270911856659267530784923638491	None
	rv_dm_stress_all	73232220378634148409122730778502925601123619338803114802573208946909478547690	None
	rv_dm_stress_all	60002898472703780961227845145072315197161150245739275235310192997722383048518	None
	rv_dm_stress_all	50310982195347831787155100560650407401573156525213427797662618658216999949815	None
	rv_dm_stress_all	14863771046210193805474308864187085992410362956663164348303858965978867592708	None
	rv_dm_stress_all	15522296186050978907459494553299993387285539252238908623670389675108141847026	None
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				4 test runs
	rv_dm_stress_all	80394794263458637290314443946106158903101658614195966644059993142744942389631	89	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	51004918360414077939080648972519576658599973488130373254738470745143779756791	95	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	20120740991838616984542747323149043219321778622138092778134990587959286858809	92	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	23561867188853887438684118111102890084770403210081809020929359740221243303102	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_dm_common_vseq] Check failed (vseq_done)				4 test runs
	rv_dm_stress_all_with_rand_reset	27251898503391493497239832273427980971864691466282177315375833541641185521083	120	UVM_INFO @ 1138581156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	7235000488976798736023114870906143098996518036246724591368823616692843174138	113	UVM_INFO @ 2154528805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	96922863154487662002296690394703093126311770931071868396992208916213901591189	116	UVM_INFO @ 8879008738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	52353572210259161332917443372218211278101725330220999901123385427360281728973	95	UVM_INFO @ 361430799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_/rtl/tlul_assert.sv,381): Assertion aKnown_AKnownEnable has failed				1 test run
	rv_dm_scanmode	94027495204459363885557591688101580221726657871317173602424948728639273352465	87	UVM_ERROR @ 624019 ps: (tlul_assert.sv:381) [ASSERT FAILED] aKnown_AKnownEnable UVM_INFO @ 624019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_rv_dm_sva_/rv_dm_enable_checker.sv,42): Assertion DebugRequestNeedsDebug_A has failed				1 test run
	rv_dm_debug_disabled	79741896303218042416095920500101475388443413020263439399458736015307997593947	89	UVM_ERROR @ 71178884 ps: (rv_dm_debug_disabled_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_debug_disabled_vseq] Check failed (rvalue == expected_output) UVM_INFO @ 71178884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				1 test run
	rv_dm_buffered_enable	98825341165043240696312941709674429658373939601017670006955143269836864621893	89	UVM_INFO @ 159455201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---