Simulation Results: rv_timer

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.29 %
  • code
  • 90.45 %
  • assert
  • 98.42 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
85.04%
V2S
100.00%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 2.000s 242.500us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 35.357us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 2.000s 14.201us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.000s 496.493us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 65.869us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 60.184us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 2.000s 14.201us 5 5 100.00
rv_timer_csr_aliasing 1.000s 65.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 1 20 5.00
rv_timer_random_reset 12.000s 19865.966us 1 20 5.00
disabled 20 20 100.00
rv_timer_disabled 5.000s 2854.392us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 383.000s 1032704.400us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 383.000s 1032704.400us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 7.000s 9038.775us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 10.453us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 13.717us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 108.568us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 108.568us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 35.357us 1 1 100.00
rv_timer_csr_rw 2.000s 14.201us 5 5 100.00
rv_timer_csr_aliasing 1.000s 65.869us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 135.676us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 35.357us 1 1 100.00
rv_timer_csr_rw 2.000s 14.201us 5 5 100.00
rv_timer_csr_aliasing 1.000s 65.869us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 135.676us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 43.608us 5 5 100.00
rv_timer_tl_intg_err 2.000s 459.418us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 459.418us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 2.000s 895.066us 2 10 20.00
max_value 1 10 10.00
rv_timer_max 2.000s 85.015us 1 10 10.00
stress_all_with_rand_reset 11 20 55.00
rv_timer_stress_all_with_rand_reset 48.000s 7785.791us 11 20 55.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:165) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 27 test runs
rv_timer_min 78528855360121007991991621647889972391366951449399473556200365761074990899461 85
UVM_INFO @ 887698356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 49148429819388528214652325983808060025881399194909065542548950257552030305821 84
UVM_INFO @ 294119964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 31788582968460027531081526021183654180393883178229865233004344414565966996952 84
UVM_INFO @ 895066384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 73475406727554849177609608547588874418010907497661653499634848402946952484422 84
UVM_INFO @ 164812047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 111211843951228712069153840660852279068285311809575761433168584666974998860380 85
UVM_INFO @ 575609961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 86812342021540204923719570896018104372758296665967216450107700597724765953213 84
UVM_INFO @ 159169098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 104733405636607257658409510086868757995557260239339778730361809877289553767086 84
UVM_INFO @ 114282553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 74703426932490821347967786386456169026388199938119683312673171254019402637500 85
UVM_INFO @ 118337213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 22902347697992233490617788837089878826381554420735961933604862710005482736023 84
UVM_INFO @ 592257386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 11697995648150651088957484918447464826284945125152269966876057736006893811141 85
UVM_INFO @ 1064457542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 87052676816851778965410959686822481210624556696812127334150766549023033902182 84
UVM_INFO @ 456843081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 114024009340698692412532032371080930181525179576438436963065739582635629717706 84
UVM_INFO @ 236381764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 106334067531598696725323820516639061312170600745394321956801099267742839128581 85
UVM_INFO @ 728236807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 32314060344189127251667692368404119384985113015020309783784832390118311964239 85
UVM_INFO @ 730048019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 44255979928246156218388631090231056652736368487919455823820057892970220680746 84
UVM_INFO @ 1819766729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 37307913500930836051650081010019456004034888621786603780232241027398351730924 84
UVM_INFO @ 19865965889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 19540892686734202137847368874609851759246611781089308506932439148652001463014 85
UVM_INFO @ 132876111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 40999429359893776061216043155335447525457771073844668424680404581778937229014 84
UVM_INFO @ 182398615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 58210408952565271718101081677171326999561306989629747202256280375208275737664 84
UVM_INFO @ 285154601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 42682637215774886148792941619658589477532373561019652005943061775859742937130 85
UVM_INFO @ 1017108474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 102156485314514769850639671077045799690753996539438620559523580567439631888845 84
UVM_INFO @ 225367328 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 13116170094539411422284046310163763527038052598524229721155480265529189016732 85
UVM_INFO @ 168862523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 30411791127546159686825891738329471487083820016389093999512663289115663611916 85
UVM_INFO @ 224341357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 111941720279472910286216194591864438696084508924372469334991773556276476787994 84
UVM_INFO @ 75684647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 108512816925594868857010044215231203859142866372015955525109630556951774331321 85
UVM_INFO @ 589814574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 24490642519032442899811465132051771714806301483187055093948543263565565016425 84
UVM_INFO @ 503226168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 84182493379383431843030362885313324867764652954385675274202392474214592297437 84
UVM_INFO @ 20916864598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 19722101259624842755835655645890306673780406055846785948915291799272880550837 84
UVM_INFO @ 85015222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 20870786180282757884758148175840949227226877725252634416020608223674689199389 84
UVM_INFO @ 171078464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 107855291101262087752629029192582783157178514263078810224282521425904507268562 84
UVM_INFO @ 46467037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 109637808515898613790296953700663666984910308094016567338616659064825824588200 84
UVM_INFO @ 524116332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 9530914062611881486789080512026479120324402366875637106983522012692833109146 84
UVM_INFO @ 48906299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 103801963965119971597608201817440404228703072032721951311040690440736486593737 84
UVM_INFO @ 170203732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 78600323749136448138329691748283405870938709850392957532109744890473551652143 85
UVM_INFO @ 54819555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 53114817057809115271056223577898046993436616824036841919160709047113133019832 84
UVM_INFO @ 50345738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 60285102751725589153709815737424795207068886430894995138734855445608001095743 84
UVM_INFO @ 44960633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [rv_timer_common_vseq] Check failed (vseq_done) 7 test runs
rv_timer_stress_all_with_rand_reset 95887458820212768704863247365890046496216833392672929843036496261325445438724 260
UVM_INFO @ 5674154548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 11255090921710293575455316257349371608454502872689497685680916838808315124356 190
UVM_INFO @ 2413738423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 7306218028123040407989234220576917137785311364391765409692855138721775679945 133
UVM_INFO @ 2255849812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 21263687937151243356140606132222720219875895182145869363306463646795977476045 218
UVM_INFO @ 1957371934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 11831490603506729406875039562909343271234870716607275271609618967753670350216 170
UVM_INFO @ 1087775245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 37568123668781751016304178783627076479262366262982388628194878248444830756408 340
UVM_INFO @ 3640391197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 85814038502045629261207042389247758746926105043359687370136460186638027996105 184
UVM_INFO @ 1383279486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
rv_timer_stress_all_with_rand_reset 96991579128194196996123727342575324629053707703792309888384052147622863774575 88
UVM_INFO @ 26958370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_stress_all_with_rand_reset 80118820912840826148503089094973859452810235142066921143031364555182192648462 135
UVM_INFO @ 1105404583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---