Simulation Results: sram_ctrl/main

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.20 %
  • code
  • 96.91 %
  • assert
  • 98.10 %
  • func
  • 96.60 %
  • block
  • 96.30 %
  • line
  • 97.05 %
  • branch
  • 94.50 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 7.000s 11035.510us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 18.302us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 24.300us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 43.490us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 72.827us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 371.726us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 24.300us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 72.827us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 294.000s 22269.504us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 148.000s 9486.996us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 67.000s 38123.386us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 245.000s 14540.729us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 245.000s 175012.566us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 64.000s 56986.693us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 50.000s 23869.477us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 71.000s 34508.644us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 8.000s 8511.543us 8 8 100.00
sram_ctrl_partial_access_b2b 355.000s 24841.992us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 7.000s 2747.918us 0 8 0.00
sram_ctrl_throughput_w_partial_write 7.000s 676.383us 0 8 0.00
sram_ctrl_throughput_w_readback 6.000s 665.188us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 23.000s 4042.502us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 5.000s 1465.311us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 513.000s 211256.150us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 42.786us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 150.287us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 150.287us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 18.302us 1 1 100.00
sram_ctrl_csr_rw 2.000s 24.300us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 72.827us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 50.058us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 1.000s 18.302us 1 1 100.00
sram_ctrl_csr_rw 2.000s 24.300us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 72.827us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 50.058us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.000s 7431.759us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 5.000s 721.713us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 1220.967us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 721.713us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 1220.967us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 23.000s 4042.502us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 23.000s 4042.502us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 24.300us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 71.000s 34508.644us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 71.000s 34508.644us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 71.000s 34508.644us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 50.000s 23869.477us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 7.000s 2807.030us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 27.000s 7431.759us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 7.000s 2665.523us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 11035.510us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 7.000s 11035.510us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 71.000s 34508.644us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 721.713us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 50.000s 23869.477us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 721.713us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 721.713us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 7.000s 11035.510us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 721.713us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 28.000s 1883.798us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 101815757047397403800223633036789692102872438067236454332450456588362234171565 86
UVM_INFO @ 1374129669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 104259897612424533733528500433845068096435469331137253926628084103786400074390 86
UVM_INFO @ 1097345027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 69974918476537910079497264918394271191471956785282629042742471748441012116866 86
UVM_INFO @ 665993666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 85792567232137701212507063684412871433913153635907000778488727279644406719799 86
UVM_INFO @ 676383421 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 7084880998083213889073910035100709368958708637892681895491991101671909090951 86
UVM_INFO @ 2627462578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 39667131341290415130912710789602436868979310322474945831378216998586711586237 86
UVM_INFO @ 657298442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 105173036134763782795163523661067142225151271223562119003941360798033080113918 86
UVM_INFO @ 660143447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 20553951143892480832165777578909099623184961371265286818531377720776864499815 86
UVM_INFO @ 2737682125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 115384390805352795124074550229180312484775593861701101411537249147835973661306 86
UVM_INFO @ 2747917760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 111740001612366078838682266230912122041765643028440871216067924133256004728477 86
UVM_INFO @ 1321436889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 34737736589712945434033189590773965821700476987673737774875773052857583833072 86
UVM_INFO @ 671187476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 24424807843086066864974781241139144271870835573355632872633962845990167709625 86
UVM_INFO @ 735693711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 22381990812076560305429382609240921446603682064861730530413101989889287741069 86
UVM_INFO @ 2053729388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 84412655606406934545631805304375212269466045159388715706547273598445608085438 86
UVM_INFO @ 4714354995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 33447892649918836823311841506486651511364386683743336021065135388600656669873 86
UVM_INFO @ 660040448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 54168073840307567203277032819590261991011882243191569938184280441039652204558 86
UVM_INFO @ 665052169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 16844181589249358751029373279605949524540572496570606364919605146015638880148 86
UVM_INFO @ 691163885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 21093054280696206543063686071511476840287747723914697387173107916384441732956 86
UVM_INFO @ 665187836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 11852663593526265970423884296099304966768838776150984368643277735242286714398 86
UVM_INFO @ 2462787597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 65171120475359909494766625038731559403644575563738612978872631323880284011770 86
UVM_INFO @ 691552350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 96098142095330522055823716756689360176595158560452634051910420977307531575249 86
UVM_INFO @ 6635802060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 33985364729888564067834686707270373695122368276986099529826983233615577295257 86
UVM_INFO @ 715884590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 30156137552618416899336274716350471034797367146627219247850807828966270876268 86
UVM_INFO @ 696149071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 97850165860107533969714312251502350976669660472025098586122321536692435216373 86
UVM_INFO @ 706773829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---