Simulation Results: sram_ctrl/ret

 
10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.39 %
  • code
  • 82.50 %
  • assert
  • 98.08 %
  • func
  • 96.60 %
  • block
  • 94.03 %
  • line
  • 95.21 %
  • branch
  • 89.83 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
97.30%
V2
84.91%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 8 8 100.00
sram_ctrl_smoke 2.000s 59.099us 8 8 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 28.439us 1 1 100.00
csr_rw 5 5 100.00
sram_ctrl_csr_rw 2.000s 17.219us 5 5 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 4.000s 440.713us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 16.782us 1 1 100.00
csr_mem_rw_with_rand_reset 4 5 80.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 37.142us 4 5 80.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
sram_ctrl_csr_rw 2.000s 17.219us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 16.782us 1 1 100.00
mem_walk 8 8 100.00
sram_ctrl_mem_walk 12.000s 830.287us 8 8 100.00
mem_partial_access 8 8 100.00
sram_ctrl_mem_partial_access 8.000s 718.226us 8 8 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 8 8 100.00
sram_ctrl_multiple_keys 17.000s 1670.995us 8 8 100.00
stress_pipeline 8 8 100.00
sram_ctrl_stress_pipeline 175.000s 12992.151us 8 8 100.00
bijection 8 8 100.00
sram_ctrl_bijection 14.000s 9250.878us 8 8 100.00
access_during_key_req 8 8 100.00
sram_ctrl_access_during_key_req 22.000s 3413.216us 8 8 100.00
lc_escalation 8 8 100.00
sram_ctrl_lc_escalation 8.000s 779.000us 8 8 100.00
executable 8 8 100.00
sram_ctrl_executable 14.000s 4655.901us 8 8 100.00
partial_access 16 16 100.00
sram_ctrl_partial_access 3.000s 114.847us 8 8 100.00
sram_ctrl_partial_access_b2b 308.000s 37795.470us 8 8 100.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 2.000s 103.725us 0 8 0.00
sram_ctrl_throughput_w_partial_write 3.000s 56.739us 0 8 0.00
sram_ctrl_throughput_w_readback 2.000s 29.714us 0 8 0.00
regwen 8 8 100.00
sram_ctrl_regwen 9.000s 2323.547us 8 8 100.00
ram_cfg 8 8 100.00
sram_ctrl_ram_cfg 2.000s 84.885us 8 8 100.00
stress_all 8 8 100.00
sram_ctrl_stress_all 67.000s 16996.171us 8 8 100.00
alert_test 10 10 100.00
sram_ctrl_alert_test 2.000s 16.071us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 1354.983us 25 25 100.00
tl_d_illegal_access 25 25 100.00
sram_ctrl_tl_errors 6.000s 1354.983us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 28.439us 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.219us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 16.782us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 53.939us 5 5 100.00
tl_d_partial_access 12 12 100.00
sram_ctrl_csr_hw_reset 2.000s 28.439us 1 1 100.00
sram_ctrl_csr_rw 2.000s 17.219us 5 5 100.00
sram_ctrl_csr_aliasing 1.000s 16.782us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 53.939us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 428.875us 5 5 100.00
tl_intg_err 30 30 100.00
sram_ctrl_sec_cm 6.000s 2002.920us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 298.602us 25 25 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 2002.920us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
sram_ctrl_tl_intg_err 4.000s 298.602us 25 25 100.00
sec_cm_ctrl_config_regwen 8 8 100.00
sram_ctrl_regwen 9.000s 2323.547us 8 8 100.00
sec_cm_readback_config_regwen 8 8 100.00
sram_ctrl_regwen 9.000s 2323.547us 8 8 100.00
sec_cm_exec_config_regwen 5 5 100.00
sram_ctrl_csr_rw 2.000s 17.219us 5 5 100.00
sec_cm_exec_config_mubi 8 8 100.00
sram_ctrl_executable 14.000s 4655.901us 8 8 100.00
sec_cm_exec_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 4655.901us 8 8 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 8 8 100.00
sram_ctrl_executable 14.000s 4655.901us 8 8 100.00
sec_cm_lc_escalate_en_intersig_mubi 8 8 100.00
sram_ctrl_lc_escalation 8.000s 779.000us 8 8 100.00
sec_cm_prim_ram_ctrl_mubi 8 8 100.00
sram_ctrl_mubi_enc_err 2.000s 274.350us 8 8 100.00
sec_cm_mem_integrity 5 5 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 428.875us 5 5 100.00
sec_cm_mem_readback 8 8 100.00
sram_ctrl_readback_err 2.000s 134.701us 8 8 100.00
sec_cm_mem_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 59.099us 8 8 100.00
sec_cm_addr_scramble 8 8 100.00
sram_ctrl_smoke 2.000s 59.099us 8 8 100.00
sec_cm_instr_bus_lc_gated 8 8 100.00
sram_ctrl_executable 14.000s 4655.901us 8 8 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 2002.920us 5 5 100.00
sec_cm_key_global_esc 8 8 100.00
sram_ctrl_lc_escalation 8.000s 779.000us 8 8 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 2002.920us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 2002.920us 5 5 100.00
sec_cm_scramble_key_sideload 8 8 100.00
sram_ctrl_smoke 2.000s 59.099us 8 8 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 2002.920us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 8 100.00
sram_ctrl_stress_all_with_rand_reset 48.000s 2342.206us 8 8 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 16 test runs
sram_ctrl_max_throughput 79042881166874183889829515355944373859665442915048547857070203712457035515495 86
UVM_INFO @ 103724501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 49046692406805912539619313785192664958915588010962966056867743469149234403649 86
UVM_INFO @ 27945909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 23722810927918521974880898101633139777004068249980562323444414042976322327873 86
UVM_INFO @ 97040041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 98262477693707475379435159798318573059820722620443729777717485514434224878667 86
UVM_INFO @ 101666937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 73769911503064528120067274956345528158233425436704815613969073002574543887475 86
UVM_INFO @ 102130048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 99815251847399561384654083830911074381420744370185422782301898885176069591351 86
UVM_INFO @ 30724068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 93482392490433240416385799568497437952203999415606493412334605103752763405321 86
UVM_INFO @ 26419758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 25987206925082507875758787859411410474178082484021414207081905803567919269938 86
UVM_INFO @ 99824685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 112093202045047047129889881277841377612886347934036899205966944969780438396275 86
UVM_INFO @ 106088494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 91758665188911386623340860108645208781611562001211314318972634483652618884841 86
UVM_INFO @ 115325317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 27740397220589863434968839035986402572531673806137654809671212056250649131234 86
UVM_INFO @ 311145566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 39447583942699101499226297815722900863398937133479060915358132348808880616968 86
UVM_INFO @ 419744824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 87534649154528566965921462192009133340613044535866420902990727568659418805917 86
UVM_INFO @ 124088481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 30890397079588318617436199424747816883237084966685742892052610118324575091330 86
UVM_INFO @ 30891005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_max_throughput 92145542846692404701976732075126397749085221348026801401313281795224088670207 86
UVM_INFO @ 27143616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 72218471188408664823040169257490585717560958030459178677023546185379554165467 86
UVM_INFO @ 56738558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 8 test runs
sram_ctrl_throughput_w_readback 97889254202900560521818232940763402406351270769400051992626684754386193461100 86
UVM_INFO @ 29714064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 15021793695249334015351241943982284388954787950768372651873682145978732183668 86
UVM_INFO @ 29808931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 111054923695975095761284910868441172415850652078142360005988841484900407377794 86
UVM_INFO @ 122414391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 78257768320743021804635669979546989079616481790651387930227793944644110957154 86
UVM_INFO @ 23503628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 18835814177213134751818667592632172142925197914827104564437994935930486045453 86
UVM_INFO @ 119401920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 113429397057594965089985593452445971428725164985282984823100107423977599308481 86
UVM_INFO @ 116132272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 8083206521494842855707605651448173925467544619582722550602476428956796788906 86
UVM_INFO @ 32119539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 41190438766866224245232264362131843772200217181141718936300494638049828477305 86
UVM_INFO @ 88453274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_driver.sv:148) [driver] Check failed seq_item_port.has_do_available() == * (* [*] vs * [*]) 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 91128890721562278407960934566793638539268418410673625955308543573692046626421 98
UVM_INFO @ 30160703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---