Simulation Results

Simulation Results: uart

10/07/2026 15:00:28 DVSim: v1.49.0 sha: 58f8fdd json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.09 %

code
92.73 %

assert
98.85 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
73.08 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		97.73%
V2S		100.00%
V3		75.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	uart_smoke	25.000s	11059.201us	10	10	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	3.000s	1030.261us	1	1	100.00
csr_rw				5	5	100.00
	uart_csr_rw	2.000s	128.626us	5	5	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	2.000s	154.961us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	314.641us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	uart_csr_mem_rw_with_rand_reset	2.000s	23.667us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	uart_csr_rw	2.000s	128.626us	5	5	100.00
	uart_csr_aliasing	1.000s	314.641us	1	1	100.00

388/397 passed

97.73 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				10	10	100.00
	uart_tx_rx	120.000s	64927.493us	10	10	100.00
parity				20	20	100.00
	uart_smoke	25.000s	11059.201us	10	10	100.00
	uart_tx_rx	120.000s	64927.493us	10	10	100.00
parity_error				20	20	100.00
	uart_intr	444.000s	335303.150us	10	10	100.00
	uart_rx_parity_err	290.000s	241679.323us	10	10	100.00
watermark				20	20	100.00
	uart_tx_rx	120.000s	64927.493us	10	10	100.00
	uart_intr	444.000s	335303.150us	10	10	100.00
fifo_full				10	10	100.00
	uart_fifo_full	386.000s	231115.064us	10	10	100.00
fifo_overflow				10	10	100.00
	uart_fifo_overflow	122.000s	364706.777us	10	10	100.00
fifo_reset				199	200	99.50
	uart_fifo_reset	428.000s	96311.901us	199	200	99.50
rx_frame_err				10	10	100.00
	uart_intr	444.000s	335303.150us	10	10	100.00
rx_break_err				10	10	100.00
	uart_intr	444.000s	335303.150us	10	10	100.00
rx_timeout				10	10	100.00
	uart_intr	444.000s	335303.150us	10	10	100.00
perf				10	10	100.00
	uart_perf	314.000s	16175.860us	10	10	100.00
sys_loopback				10	10	100.00
	uart_loopback	16.000s	8967.736us	10	10	100.00
line_loopback				10	10	100.00
	uart_loopback	16.000s	8967.736us	10	10	100.00
rx_noise_filter				4	10	40.00
	uart_noise_filter	241.000s	112838.237us	4	10	40.00
rx_start_bit_filter				10	10	100.00
	uart_rx_start_bit_filter	20.000s	41920.393us	10	10	100.00
tx_overide				10	10	100.00
	uart_tx_ovrd	29.000s	6658.523us	10	10	100.00
rx_oversample				10	10	100.00
	uart_rx_oversample	35.000s	5416.238us	10	10	100.00
long_b2b_transfer				10	10	100.00
	uart_long_xfer_wo_dly	1338.000s	177637.279us	10	10	100.00
stress_all				8	10	80.00
	uart_stress_all	800.000s	415642.205us	8	10	80.00
alert_test				10	10	100.00
	uart_alert_test	2.000s	150.099us	10	10	100.00
intr_test				10	10	100.00
	uart_intr_test	2.000s	30.037us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	uart_tl_errors	3.000s	129.849us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	uart_tl_errors	3.000s	129.849us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	uart_csr_hw_reset	3.000s	1030.261us	1	1	100.00
	uart_csr_rw	2.000s	128.626us	5	5	100.00
	uart_csr_aliasing	1.000s	314.641us	1	1	100.00
	uart_same_csr_outstanding	2.000s	31.108us	5	5	100.00
tl_d_partial_access				12	12	100.00
	uart_csr_hw_reset	3.000s	1030.261us	1	1	100.00
	uart_csr_rw	2.000s	128.626us	5	5	100.00
	uart_csr_aliasing	1.000s	314.641us	1	1	100.00
	uart_same_csr_outstanding	2.000s	31.108us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	uart_sec_cm	2.000s	42.181us	5	5	100.00
	uart_tl_intg_err	2.000s	180.855us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	uart_tl_intg_err	2.000s	180.855us	25	25	100.00

15/20 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				15	20	75.00
	uart_stress_all_with_rand_reset	55.000s	21477.011us	15	20	75.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:395) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				5 test runs
	uart_noise_filter	5546982648163728718682440703051321881596283380524063520083626673537548878904	86	UVM_ERROR @ 8535472342 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 8544209254 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 8552946166 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 8561683078 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all	71647269110069646827605375064039833407367946486267805900547076252739661290892	111	UVM_ERROR @ 224523506911 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 225223894013 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 5 UVM_ERROR @ 225223937491 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 225224024447 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (118 [0x76] vs 47 [0x2f]) reg name: uart_reg_block.rdata
	uart_noise_filter	64260464687807454922686948894002651433162933842918566551097690612563439938824	83	UVM_ERROR @ 79645370 ps: (uart_scoreboard.sv:446) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr UVM_ERROR @ 79645370 ps: (uart_scoreboard.sv:448) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr UVM_ERROR @ 103043142 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 103063550 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	7308522873539383830412953097579465601919432939121003144252041718617111238190	83	UVM_ERROR @ 21176999 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 21176999 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 24677027 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 24677027 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all_with_rand_reset	96875093818220546653477050766942111517669660141307608862020793207585420219045	86	UVM_INFO @ 20433729 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 1/5 UVM_INFO @ 20825031 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Stress w/ reset is done for run 1/5
UVM_ERROR (uart_scoreboard.sv:502) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				5 test runs
	uart_noise_filter	111758096262410563597183723309322512992754060437621603109480733763711234096168	84	UVM_ERROR @ 11829649049 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 11829659253 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (139 [0x8b] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 11925607465 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 11925607465 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	114705938344744579693629178666478879916879185765407863676687633542465059556114	84	UVM_ERROR @ 815949797 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 816026721 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 63 [0x3f]) reg name: uart_reg_block.rdata UVM_ERROR @ 816103645 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 816180569 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
	uart_stress_all_with_rand_reset	91223310586962769110865637613717354275734783001769398783979610460836501561080	101	UVM_ERROR @ 2901705795 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 2902277227 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata UVM_ERROR @ 3056421009 ps: (uart_scoreboard.sv:379) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 3056421009 ps: (uart_scoreboard.sv:395) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	30064074887747947108414351316737700643292135158721300960429479817120006124057	85	UVM_ERROR @ 13962071551 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 13962081652 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata UVM_ERROR @ 14100970402 ps: (uart_scoreboard.sv:502) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 14100990604 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_stress_all	21254747146830953459399489684539972936390331361655392861428605443712453436974	107	UVM_ERROR @ 34140862011 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 34140925167 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (135 [0x87] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 34140946219 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 34140988323 ps: (uart_scoreboard.sv:532) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (135 [0x87] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR (cip_base_vseq.sv:1287) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	uart_stress_all_with_rand_reset	39281742650024909231676122028088333112194697758054149263854010322307023397334	130	UVM_ERROR @ 5617340052 ps: (cip_base_vseq.sv:1200) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. UVM_INFO @ 5617340052 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 3/10 UVM_INFO @ 5617358952 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2
UVM_ERROR (cip_base_vseq.sv:1200) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	uart_stress_all_with_rand_reset	4349441100791640494010697971857570134950771372572097471108467714024889993779	119	UVM_INFO @ 3729117074 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 3/5 UVM_INFO @ 3729273324 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Stress w/ reset is done for run 3/5
UVM_ERROR (uart_scoreboard.sv:448) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: TxEmpty				1 test run
	uart_stress_all_with_rand_reset	62835188579800964206671554704141905145952888486748959969270861988113528014934	100	UVM_INFO @ 187708480 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/351 UVM_INFO @ 225510998 ps: (cip_base_vseq.sv:1203) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Issuing reset for run 3/10 UVM_INFO @ 225927668 ps: (cip_base_vseq.sv:1224) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				1 test run
	uart_fifo_reset	111682237206902773816846332769096227330994501013475629413892006619501583941715	90	UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---