Simulation Results

Simulation Results: ac_range_check

17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
83.29 %

code
93.53 %

assert
97.75 %

func
58.58 %

block
99.10 %

line
99.93 %

branch
98.24 %

toggle
82.43 %

Validation stages

V1		94.34%
V2		96.59%
V2S		100.00%
V3		100.00%
unmapped		100.00%

50/53 passed

94.34 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_smoke				19	20	95.00
	ac_range_check_smoke	55.000s	1650.116us	19	20	95.00
ac_range_check_smoke_racl				18	20	90.00
	ac_range_check_smoke_racl	74.000s	2650.758us	18	20	90.00
csr_hw_reset				1	1	100.00
	ac_range_check_csr_hw_reset	2.000s	21.516us	1	1	100.00
csr_rw				5	5	100.00
	ac_range_check_csr_rw	3.000s	163.355us	5	5	100.00
csr_bit_bash				1	1	100.00
	ac_range_check_csr_bit_bash	39.000s	1413.182us	1	1	100.00
csr_aliasing				1	1	100.00
	ac_range_check_csr_aliasing	45.000s	1226.383us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	ac_range_check_csr_mem_rw_with_rand_reset	3.000s	35.061us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	ac_range_check_csr_rw	3.000s	163.355us	5	5	100.00
	ac_range_check_csr_aliasing	45.000s	1226.383us	1	1	100.00

85/88 passed

96.59 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
ac_range_check_lock_range				20	20	100.00
	ac_range_check_lock_range	4.000s	121.757us	20	20	100.00
ac_range_bypass_enable				1	1	100.00
	ac_range_check_bypass	65.000s	1699.050us	1	1	100.00
stress_all				7	10	70.00
	ac_range_check_stress_all	227.000s	32864.605us	7	10	70.00
alert_test				10	10	100.00
	ac_range_check_alert_test	27.000s	284.490us	10	10	100.00
intr_test				10	10	100.00
	ac_range_check_intr_test	2.000s	15.161us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	ac_range_check_tl_errors	6.000s	172.055us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	ac_range_check_tl_errors	6.000s	172.055us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	ac_range_check_csr_hw_reset	2.000s	21.516us	1	1	100.00
	ac_range_check_csr_rw	3.000s	163.355us	5	5	100.00
	ac_range_check_csr_aliasing	45.000s	1226.383us	1	1	100.00
	ac_range_check_same_csr_outstanding	6.000s	465.173us	5	5	100.00
tl_d_partial_access				12	12	100.00
	ac_range_check_csr_hw_reset	2.000s	21.516us	1	1	100.00
	ac_range_check_csr_rw	3.000s	163.355us	5	5	100.00
	ac_range_check_csr_aliasing	45.000s	1226.383us	1	1	100.00
	ac_range_check_same_csr_outstanding	6.000s	465.173us	5	5	100.00

V2S

70/70 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	ac_range_check_shadow_reg_errors	25.000s	4771.823us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	ac_range_check_shadow_reg_errors	25.000s	4771.823us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	ac_range_check_shadow_reg_errors	25.000s	4771.823us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	ac_range_check_shadow_reg_errors	25.000s	4771.823us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	ac_range_check_shadow_reg_errors_with_csr_rw	116.000s	13829.473us	20	20	100.00
tl_intg_err				30	30	100.00
	ac_range_check_sec_cm	2.000s	26.846us	5	5	100.00
	ac_range_check_tl_intg_err	14.000s	1615.964us	25	25	100.00

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				10	10	100.00
	ac_range_check_stress_all_with_rand_reset	368.000s	2446.157us	10	10	100.00

unmapped

20/20 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				20	20	100.00
	ac_range_check_smoke_high_threshold	41.000s	3128.148us	20	20	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (ac_range_check_scoreboard.sv:374) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: ac_range_check_reg_block.intr_state				5 test runs
	ac_range_check_stress_all	91369056373148031116982081980122384377233316911841328450869126167526692810307	14129	UVM_INFO @ 1639182008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_stress_all	25608384321626287019838012320770091582710954679833672724798525491501614701131	4269	UVM_INFO @ 5535744082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke	91320439232573806106033947257944084859500812022945119196505858433774813300339	4184	UVM_INFO @ 5468399480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke_racl	98894224401836275827867845590685250464291440135406212528816376823001835399574	4180	UVM_INFO @ 7528330662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	ac_range_check_smoke_racl	37973094025007210707093499355918769266107600602065388184149935407656937900415	4132	UVM_INFO @ 2780636016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_scoreboard.sv:166) [scoreboard] Unable to get any item from tl_unfilt_d_chan_fifo.				1 test run
	ac_range_check_stress_all	37812980799942138399697610719489885710776116077537138973387196922192960745302	9536	UVM_INFO @ 100557346931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---