Simulation Results

Simulation Results: clkmgr

17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
77.66 %

code
69.18 %

assert
90.08 %

func
73.71 %

line
81.76 %

branch
86.53 %

cond
79.88 %

toggle
97.74 %

FSM
0.00 %

Validation stages

V1		69.57%
V2		68.38%
V2S		29.52%
V3		0.00%

16/23 passed

69.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.290s	91.775us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.190s	18.200us	1	1	100.00
csr_rw				3	5	60.00
	clkmgr_csr_rw	1.490s	46.263us	3	5	60.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	3.520s	106.544us	0	1	0.00
csr_aliasing				0	1	0.00
	clkmgr_csr_aliasing	0.940s	10.200us	0	1	0.00
csr_mem_rw_with_rand_reset				2	5	40.00
	clkmgr_csr_mem_rw_with_rand_reset	2.070s	68.851us	2	5	40.00
regwen_csr_and_corresponding_lockable_csr				3	6	50.00
	clkmgr_csr_rw	1.490s	46.263us	3	5	60.00
	clkmgr_csr_aliasing	0.940s	10.200us	0	1	0.00

80/117 passed

68.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.850s	61.594us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	4.940s	261.961us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	2.320s	104.993us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.290s	91.775us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	2.090s	85.452us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.030s	8.061us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	2.090s	85.452us	0	10	0.00
stress_all				1	10	10.00
	clkmgr_stress_all	4.390s	244.501us	1	10	10.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.770s	61.159us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	17.110s	963.439us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	17.110s	963.439us	25	25	100.00
tl_d_outstanding_access				4	12	33.33
	clkmgr_csr_hw_reset	1.190s	18.200us	1	1	100.00
	clkmgr_csr_rw	1.490s	46.263us	3	5	60.00
	clkmgr_csr_aliasing	0.940s	10.200us	0	1	0.00
	clkmgr_same_csr_outstanding	1.140s	16.353us	0	5	0.00
tl_d_partial_access				4	12	33.33
	clkmgr_csr_hw_reset	1.190s	18.200us	1	1	100.00
	clkmgr_csr_rw	1.490s	46.263us	3	5	60.00
	clkmgr_csr_aliasing	0.940s	10.200us	0	1	0.00
	clkmgr_same_csr_outstanding	1.140s	16.353us	0	5	0.00

V2S

31/105 passed

29.52 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	30	0.00
	clkmgr_sec_cm	120.810s	10006.122us	0	5	0.00
	clkmgr_tl_intg_err	2.110s	74.557us	0	25	0.00
shadow_reg_update_error				18	20	90.00
	clkmgr_shadow_reg_errors	2200.560s	200000.000us	18	20	90.00
shadow_reg_read_clear_staged_value				18	20	90.00
	clkmgr_shadow_reg_errors	2200.560s	200000.000us	18	20	90.00
shadow_reg_storage_error				18	20	90.00
	clkmgr_shadow_reg_errors	2200.560s	200000.000us	18	20	90.00
shadowed_reset_glitch				18	20	90.00
	clkmgr_shadow_reg_errors	2200.560s	200000.000us	18	20	90.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.520s	45.529us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	2.110s	74.557us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	2.090s	85.452us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.030s	8.061us	0	10	0.00
sec_cm_meas_config_shadow				18	20	90.00
	clkmgr_shadow_reg_errors	2200.560s	200000.000us	18	20	90.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	3.020s	154.931us	10	10	100.00
sec_cm_jitter_config_mubi				3	5	60.00
	clkmgr_csr_rw	1.490s	46.263us	3	5	60.00
sec_cm_idle_ctr_redun				0	5	0.00
	clkmgr_sec_cm	120.810s	10006.122us	0	5	0.00
sec_cm_meas_config_regwen				3	5	60.00
	clkmgr_csr_rw	1.490s	46.263us	3	5	60.00
sec_cm_clk_ctrl_config_regwen				3	5	60.00
	clkmgr_csr_rw	1.490s	46.263us	3	5	60.00
prim_count_check				0	5	0.00
	clkmgr_sec_cm	120.810s	10006.122us	0	5	0.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.410s	33.105us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	4.490s	132.968us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				26 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	3945809407458862920511752553971979198842323512126664348246853629116520653039	75	UVM_INFO @ 5465271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	4484598165802801886643102092657475312788684409598318598325690373696099766563	86	UVM_INFO @ 20298097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	10388272479361785152551950627614161699323890480576989760870343572313080732458	75	UVM_INFO @ 4642074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	80116687881179274869500499041617878016615585144928358209850062857937069662174	100	UVM_INFO @ 74557209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	23712665518956627550639314925040488478667112194206036713966693951818287236996	75	UVM_INFO @ 4689005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	21572569773663198556757468864158486084728257875074771776992204097447233046507	75	UVM_INFO @ 1590751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	112181270872415642704147492902050934113388215860151922372366507867446855689835	82	UVM_INFO @ 6446688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	98426686965312544297812191305210245337785435170792519295285853755830715190570	75	UVM_INFO @ 12968043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	82870609453158023246512388962526005060233418424204440579268351834527100932179	90	UVM_INFO @ 14889789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	31036442856766977735871887257925113493193029650880415787544144472692971584043	75	UVM_INFO @ 2139914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	85192081457046698156108153136520569972270720834980653473362022136889707404714	82	UVM_INFO @ 8377137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	109068524133834776798136761653984994521510639872253707205569998614589847803354	78	UVM_INFO @ 8104191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	111943848688050023933710862218885262914056133355067454150294523235509650577785	75	UVM_INFO @ 6935355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	72587167956897903654083888408102082460893350879116168894286253415693651213849	75	UVM_INFO @ 4413054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	94347193009064972658507180271227937441968336486031401458378228027802174087857	75	UVM_INFO @ 2631208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	28466429405074915428009032160041248371383839948952235047885362381296577073833	75	UVM_INFO @ 11833826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	62109086167106953945101647140921106966479267866112908359982818307124688458942	75	UVM_INFO @ 5609965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	84761890280611886068066238436021507097857829351229978687379370973252155049429	90	UVM_INFO @ 22089996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	53001607907692461187088053629942898054803560345631097375373637477736399561714	82	UVM_INFO @ 3348826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	12439899305830584115163579508065641357162699956532048922459640951260326910101	75	UVM_INFO @ 3835196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	62544104592330559864777018516628025586203218363212756017576110682055566367207	75	UVM_INFO @ 3522836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	69294901786864914451172413911882399915137971485228265932032873430486695575355	75	UVM_INFO @ 23632444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	74326197728818505210447330948615383688761442882161514804793924984195030093846	75	UVM_INFO @ 16410131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	29796681848910028812016822519179057398188245854357262226991322179554088174049	94	UVM_INFO @ 18123173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	44643839638712511543740810762631708447040865309692626430893192056891254172466	111	UVM_INFO @ 37941825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	84277834643437927024317243269557339472211910370725099423194537836342221977521	86	UVM_INFO @ 23276683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				25 test runs
	clkmgr_csr_aliasing	57977954345662430449835662244912541163828258124979566476907709844737076668523	75	UVM_INFO @ 10199715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	105057966294979902728133009100626811758247115876824862584406544105481884144276	86	UVM_INFO @ 19100264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	76148526426984962077796414871514381583237602404473401811894438868055366186597	76	UVM_INFO @ 21042856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	3694432222499443828258210755103694855851700548952370091713434850593247119301	75	UVM_INFO @ 11488277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	57132978160936701187622290519972534898687808995928311529210342478195640392386	89	UVM_INFO @ 20456968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	43981468918058717383176640601092959699114875302175594289466944024285020106195	76	UVM_INFO @ 6115145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	29834904046093903819443599460067733565524886056783910022694932774454205506833	75	UVM_INFO @ 45529352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	15431919962893919578698260864696624636945540991678999784065706451318841625172	86	UVM_INFO @ 18475726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	9971961644138240909910604104325219003230920602224685446773232071414443720132	75	UVM_INFO @ 2819742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	68359814110791700628279835731773223156992110451999406047650950548152420836106	76	UVM_INFO @ 5586239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	4558650776840387787654599676253473856200172456358091086267132989598041088036	75	UVM_INFO @ 3739823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	51210063131020533876522131163311043071599661883671888953531913459249162771147	75	UVM_INFO @ 3218445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	61670489132748665292607554794647856604692431982123654523910769851352684978462	78	UVM_INFO @ 4209820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	48235802278585593138569859650534153145910386654165842783542708170424988787885	75	UVM_INFO @ 12022384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	89946178405441487543525718678663000667601619145347371902177864427016586550544	78	UVM_INFO @ 7104859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	110413939313041284920742362691325236437224355392258831116704217727878527515935	75	UVM_INFO @ 5725355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	12318431228788362910865817836394265870306068315849615980422230354632893314959	109	UVM_INFO @ 50363514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	85684113873624081675026860898497541989629671857804152366350523370003432920065	97	UVM_INFO @ 16483686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	52203962864543360999819954261688838386865366983817390095167543725504579559794	75	UVM_INFO @ 2207998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	60215934360973822786364613188940402625490307203913943420735530180945814181688	75	UVM_INFO @ 3176087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	73365912032049830743990358741095347582415819187065905091358327697582654992195	101	UVM_INFO @ 14411504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	37949569034806802915078646682550446447649937854547740564221393810650291006650	75	UVM_INFO @ 2416325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	89303296315889410799895170653361291957021453466095453198379941360934773052078	85	UVM_INFO @ 3128332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	38188625193191265441184262071815703052288195579822524306297424001350656130327	101	UVM_INFO @ 56505074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	106205108092878286882570410847624933143684803727217097771177641380533087983670	89	UVM_INFO @ 20447484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				22 test runs
	clkmgr_frequency_timeout	102068679320121613680977599802301917408393172866074170286069134437829300949425	78	UVM_INFO @ 3810873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	81580213135677757347385557439872945709932699060713365715053663290430499602583	78	UVM_INFO @ 4622246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	109423046822653441264826592971238435502167439176844824931913022804324093630552	123	UVM_INFO @ 114073981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	93643038800756177627630180119216823536499948542628842393098762951402823342241	78	UVM_INFO @ 8061243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	89247769129354964863287663057839361893296592159988617655782948595436687818735	79	UVM_INFO @ 12452428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	63425390663442318147214653430700230908150394850868711095144178928066225835036	77	UVM_INFO @ 14966215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	48372973124757731157426948015975918363774293532972506069530815378003892355417	78	UVM_INFO @ 2587846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	44024248106455620564437133754441347606393010273893906268772329594993839989818	78	UVM_INFO @ 3210368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	87240383561195898289491210430385001589735804827096002263738009968747535748561	78	UVM_INFO @ 6404457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	78498777331960754643939495295757482361824522948362359518140286132633404652606	78	UVM_INFO @ 5081572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	113069610294406985750870804971216518787979621397544005245963650315080840488004	79	UVM_INFO @ 22964330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	97634826405782634032768679249691543032616828488592817612207886850247108320750	225	UVM_INFO @ 103568544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	96129854049782897003951294678971948228884825025975707117165992019004164648999	77	UVM_INFO @ 4135582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	97696473886371936336887302999139606973638509414242135203916092063395185132877	93	UVM_INFO @ 27881246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	47841053175170431943077735230290949327122913236158467871840758080697688239292	77	UVM_INFO @ 11069776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	115146463432861959684205413081358334664492929291685676487024863983224678067758	77	UVM_INFO @ 4137793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	24825939490370181556954950850591740108345906091247820319639783186239560202782	95	UVM_INFO @ 105743555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	17016550260605797636512426822740342111888195598403891362109493865241935338275	78	UVM_INFO @ 4602880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	45035490037316047646110799391801394170975748225379015016717295319811659640244	78	UVM_INFO @ 2893939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	46797234037829975747837431508593862167184057241047236143784188370013295697709	138	UVM_INFO @ 271512825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	38029072725002646786660683818388982070426024887717869220761384298410782148973	78	UVM_INFO @ 2534234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	65277919224853694741423008631210431198597980652283107183425065873416270906049	85	UVM_INFO @ 132968003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				17 test runs
	clkmgr_frequency	3936258288124533540943619379243856594982504821750298311322420666128065662985	75	UVM_INFO @ 8085472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	100058803017573395441592397023805569359659630057437213885800413465379087953468	79	UVM_INFO @ 10321256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	80626445306666563973139706911443535533930489121627618049860168034828246364252	78	UVM_INFO @ 23730602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	19237210032018347408713107747457332102538804316820931293146207788749028844288	75	UVM_INFO @ 12428342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	19943155502945952185415321351644415987171851364323427425232896684907982110240	76	UVM_INFO @ 15022591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	57948249886544644748085993718215932429791835315399435797144246445852210805276	76	UVM_INFO @ 21493681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	47702703947895272469095331384352197220327518363411149604232079133063951904745	76	UVM_INFO @ 8847706 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	14871131995235489785092211210308536932821924418738675478959649406988148026242	89	UVM_INFO @ 63963085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	92971714622326066623789672058718618339857770589828202360875890754104240650057	75	UVM_INFO @ 14254084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	3777818955739030892204612784864034126028731398168675832467610664876066877391	78	UVM_INFO @ 4740225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	78421611929018683596369162404682752049514557547060807850014094520886440563987	76	UVM_INFO @ 13028429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	35923447508224799174584537108601016387148852891300352999504792502698006656435	76	UVM_INFO @ 6707396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	42002526867393427314846742699878325146771196687551387271231449675310101447582	76	UVM_INFO @ 12314606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	38570748025821076302763405991817897319804462307707500334974871830093587530659	75	UVM_INFO @ 4166399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	71643752726317544649469982978511286432369343630250572206351616324670917348375	106	UVM_INFO @ 102016076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	1675084256461011055950145891098780068573679746510901249525790039396020155771	76	UVM_INFO @ 85451811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	107041476160908690865187455960900865862486438140661698080105335690808802902636	144	UVM_INFO @ 244500760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	44446699088010780054466790067730694627783795743245548700975313160332077173448	75	UVM_INFO @ 9991219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	79982610978571752462011169916743701221327053565158496298338396734184743868276	75	UVM_INFO @ 16352856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	42148932534849940701521824614026583336620080225348144618282443575341564737163	75	UVM_INFO @ 11045488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	7698953681581872916222195758463011663014986511292301004648741018816809202201	75	UVM_INFO @ 7418258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	63526973879240220174435064684612574029584658023981702379515620219967865192243	75	UVM_INFO @ 8201015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				5 test runs
	clkmgr_regwen	73771431191274476960447160473735485500712890857726756119806355535781417231148	74	UVM_INFO @ 7593696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	102059739358556633325752980295483454637043116879708296727666431136021530590105	74	UVM_INFO @ 8709210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	108796098381727986339343895536152320196552706506517806703392358142498552011090	74	UVM_INFO @ 4019518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	15834679312497710542732601944641482997379415466192599938192736433008050146258	74	UVM_INFO @ 4943677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	73721881632440662651020505118038056680767245182969821725713084170967624977529	74	UVM_INFO @ 8230704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				4 test runs
	clkmgr_regwen	29637494571546301292783870656063217139057815702842994156379757364177158543867	74	UVM_INFO @ 7713532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	41916752856410556219086045679982331741991500217540250671356989859453773656709	74	UVM_INFO @ 3242875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	32636213662107732426276056409825322933433061144600994841694068020645047607365	74	UVM_INFO @ 11795163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	57440567007946629197067627315745921708339328149764281853395014861851046252999	74	UVM_INFO @ 19560261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault				3 test runs
	clkmgr_sec_cm	82202165605005488195989716371585426514905955016851134473574571322824126097958	139	UVM_INFO @ 10144310968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	10964003086101167028404429911892663779776129667898238350128412488702080805056	115	UVM_INFO @ 10049404130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	13671810457926543407595747350478654042931936956444786081217858360072381637444	80	UVM_INFO @ 10006122270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				2 test runs
	clkmgr_sec_cm	110657815954413164443913093608789740486827379338869154114382630037234600877089	106	UVM_INFO @ 32911513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_sec_cm	46082841132104739343480892821361068498877929087580855877415121112842733333989	81	UVM_INFO @ 5649818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	clkmgr_shadow_reg_errors	39223059137615268922105963151584303489480557256684554546540158018709312869149	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors	105179830286219238460991678657483448223454842546665835126370863783296174061915	75	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	75739866769340736160648205682522522328879649234331907338052948232517625164326	75	UVM_INFO @ 106544266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:257) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en				1 test run
	clkmgr_regwen	111229194320202963285901498831326664664094288474472268394446222145779627347196	74	UVM_INFO @ 33105354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---