Simulation Results

Simulation Results: csrng

17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.77 %

code
96.17 %

assert
96.94 %

func
91.21 %

block
98.49 %

line
99.50 %

branch
96.30 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		98.16%
V2S		98.91%
V3		0.00%

38/38 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				25	25	100.00
	csrng_smoke	4.000s	52.537us	25	25	100.00
csr_hw_reset				1	1	100.00
	csrng_csr_hw_reset	34.000s	17.056us	1	1	100.00
csr_rw				5	5	100.00
	csrng_csr_rw	34.000s	42.995us	5	5	100.00
csr_bit_bash				1	1	100.00
	csrng_csr_bit_bash	65.000s	2156.103us	1	1	100.00
csr_aliasing				1	1	100.00
	csrng_csr_aliasing	38.000s	85.123us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	csrng_csr_mem_rw_with_rand_reset	36.000s	159.655us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	csrng_csr_rw	34.000s	42.995us	5	5	100.00
	csrng_csr_aliasing	38.000s	85.123us	1	1	100.00

1283/1307 passed

98.16 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				200	200	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
alerts				500	500	100.00
	csrng_alert	46.000s	373.522us	500	500	100.00
err				500	500	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
cmds				2	25	8.00
	csrng_cmds	206.000s	13970.013us	2	25	8.00
life cycle				2	25	8.00
	csrng_cmds	206.000s	13970.013us	2	25	8.00
stress_all				24	25	96.00
	csrng_stress_all	2146.000s	167210.942us	24	25	96.00
intr_test				10	10	100.00
	csrng_intr_test	5.000s	58.699us	10	10	100.00
alert_test				10	10	100.00
	csrng_alert_test	35.000s	26.646us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	csrng_tl_errors	15.000s	816.559us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	csrng_tl_errors	15.000s	816.559us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	csrng_csr_hw_reset	34.000s	17.056us	1	1	100.00
	csrng_csr_rw	34.000s	42.995us	5	5	100.00
	csrng_csr_aliasing	38.000s	85.123us	1	1	100.00
	csrng_same_csr_outstanding	4.000s	130.857us	5	5	100.00
tl_d_partial_access				12	12	100.00
	csrng_csr_hw_reset	34.000s	17.056us	1	1	100.00
	csrng_csr_rw	34.000s	42.995us	5	5	100.00
	csrng_csr_aliasing	38.000s	85.123us	1	1	100.00
	csrng_same_csr_outstanding	4.000s	130.857us	5	5	100.00

V2S

1271/1285 passed

98.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	csrng_sec_cm	13.000s	639.434us	5	5	100.00
	csrng_tl_intg_err	23.000s	635.240us	25	25	100.00
sec_cm_config_regwen				17	30	56.67
	csrng_regwen	3.000s	68.984us	12	25	48.00
	csrng_csr_rw	34.000s	42.995us	5	5	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	46.000s	373.522us	500	500	100.00
sec_cm_intersig_mubi				24	25	96.00
	csrng_stress_all	2146.000s	167210.942us	24	25	96.00
sec_cm_main_sm_fsm_sparse				705	705	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
	csrng_sec_cm	13.000s	639.434us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				705	705	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
	csrng_sec_cm	13.000s	639.434us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				705	705	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
	csrng_sec_cm	13.000s	639.434us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				705	705	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
	csrng_sec_cm	13.000s	639.434us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				705	705	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
	csrng_sec_cm	13.000s	639.434us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	46.000s	373.522us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				700	700	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
sec_cm_constants_lc_gated				24	25	96.00
	csrng_stress_all	2146.000s	167210.942us	24	25	96.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	46.000s	373.522us	500	500	100.00
sec_cm_tile_link_bus_integrity				25	25	100.00
	csrng_tl_intg_err	23.000s	635.240us	25	25	100.00
sec_cm_aes_cipher_fsm_sparse				705	705	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
	csrng_sec_cm	13.000s	639.434us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				700	700	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				700	700	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				700	700	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				705	705	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00
	csrng_sec_cm	13.000s	639.434us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				700	700	100.00
	csrng_intr	21.000s	180.732us	200	200	100.00
	csrng_err	24.000s	28.514us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	3600.000s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				21 test runs
	csrng_cmds	38988648654671445353014361635811717530256019841538635772273059756238486423857	100	UVM_INFO @ 822437325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	60667725718876512685924621522917856604294463962180584770874554584433163155274	100	UVM_INFO @ 100806301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	7887516295615134786472193555905144137076513846334618012664513847887652675355	110	UVM_INFO @ 527621493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	59163217269990127935546952945009021069121609490330206809978978311811999418013	100	UVM_INFO @ 251076331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	67562132638301768145711240808155572950192104389706217796341534043992739504265	100	UVM_INFO @ 66096678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	81896911895491820509294379062978969280044136699604753568322393743914319100143	100	UVM_INFO @ 39377757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	98306590206559333158866552278493872386210520215703869734468277796546573361275	100	UVM_INFO @ 136711673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	103300092507439479523354313826735215406308657769497359000094645978738107761213	130	UVM_INFO @ 310661192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	33783629099976967357576021355929801643085740033573429460744586024995271732102	100	UVM_INFO @ 121452866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	10078372098919498911419829304057154120893052509445538886167882841283574453509	100	UVM_INFO @ 689783604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	19768189131636975567807445441800620176933122346438275275845636265707416024201	109	UVM_INFO @ 105659175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46109304577474315759529861191826617004083088888843694882438425813392403509823	110	UVM_INFO @ 781435337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	32197034056952214982635362281502834410114457991021914993370447528042054672505	110	UVM_INFO @ 143715176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	20775450703533646235922816826980028836552190757471729781213388175017507386543	100	UVM_INFO @ 138225599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	97213529702859824223494195300310262549942844232355032810089973693736539388057	100	UVM_INFO @ 924829103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	62877443573846542186003253772979432445581474155226190518857366832540012200108	110	UVM_INFO @ 221880970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	105396894087062690667275710696587566967990720216427664088970905720134695708402	100	UVM_INFO @ 175616182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	96725241285425739453532268537040948600843046614308647423547713335999333075877	100	UVM_INFO @ 30110251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	86788499827304017080770719031623602247782902436924778979230432611249042023986	109	UVM_INFO @ 17672594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	102257227627632137446252334036349718954571925359033914348349099781187108405303	100	UVM_INFO @ 378080785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	93789463142737542792883127945922712393641813366201433786222018009333401412476	100	UVM_INFO @ 173819551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE				10 test runs
	csrng_regwen	113095292652977763962107578083005814713920401232785718288825381948672556360031	99	UVM_INFO @ 11051750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	5599794673363101064643450445929499363296946748061905298676131372855538938059	99	UVM_INFO @ 3210933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	96562405199970985645833645825507892302761958198290033951377459553585666415201	99	UVM_INFO @ 3451490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	107312283953371942158386289325483240284820159472026386642848014696964647035760	99	UVM_INFO @ 5533736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	45745649931780801218580823948600801045402232307138979177909914293268657659928	99	UVM_INFO @ 13085898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	102983095209917281799071546134879552715580446305595014559974121528107333013183	99	UVM_INFO @ 7142252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	111486404224805722001418708879070623362841649634191610882835809024044301506990	99	UVM_INFO @ 12719725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	2467327687983219462495465461505981389745658281745058433864239622789608943326	99	UVM_INFO @ 6491865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	17611661698401866671026758948145980627191784978184355318361043159315232417493	99	UVM_INFO @ 19303501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	43166901576366418459416737285453341400412637374442883673363890068693847662151	99	UVM_INFO @ 1329161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				5 test runs
	csrng_stress_all_with_rand_reset	87654189248552104081326254148925748670116569174108734136078239233596368312911	120	UVM_INFO @ 57864960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	11550361872433556301334604602260580777958413261191786011919051893471665009876	119	UVM_INFO @ 65138075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	46031761327579570492750544777896365231680436194010533456909571245032010758912	139	UVM_INFO @ 2816613419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	15936456138238284788616663357886836197298816207998241040813533035229017318023	137	UVM_INFO @ 5766744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	29350961703194836783209641560830092072952551622054645621626177894151761366258	207	UVM_INFO @ 2880453736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				3 test runs
	csrng_stress_all_with_rand_reset	82824536549887356780785612768498240907481962903069031995216796294411045853503	108	UVM_INFO @ 913624842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	92058852137939423930159760186307190358453432284645317281303042486266818889428	151	UVM_INFO @ 42294947083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	18673616212337393542780739464925884837109670347305134442613882351867631311479	160	UVM_INFO @ 1895442269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE				3 test runs
	csrng_regwen	79731178455144593699669870670026996496050022639127517114741278220363374795796	99	UVM_INFO @ 4985837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	27523531789575956775071947828221493268242088265999699793401222751994172968011	99	UVM_INFO @ 1731961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_regwen	56190624544629995913909163287887925146744704497852139799981571543666702268920	99	UVM_INFO @ 3394120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	csrng_stress_all_with_rand_reset	48448682005058656034404565510534548877572492372682371713095027810742313215825	None
	csrng_stress_all_with_rand_reset	91549207637814956908873915158055794107953391916078647310388614046590037968294	None
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				2 test runs
	csrng_cmds	106572703012055638946177216549418596071003273950204634377285623487518739329997	103	UVM_INFO @ 540844143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	24973721871223149660503978165661035619986302449613044231488817144790382681460	103	UVM_INFO @ 289450774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:358) [cfg] Check failed hw_v == * (* [] vs [*])				1 test run
	csrng_stress_all_with_rand_reset	93626446703987305286376003727884027773130101097932346445313925212575444767900	105	UVM_INFO @ 25196305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---