| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| unmapped |
|
96.77% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_smoke | 25 | 25 | 100.00 | |||
| dma_memory_smoke | 8.000s | 1342.161us | 25 | 25 | 100.00 | |
| dma_handshake_smoke | 25 | 25 | 100.00 | |||
| dma_handshake_smoke | 8.000s | 351.170us | 25 | 25 | 100.00 | |
| dma_generic_smoke | 50 | 50 | 100.00 | |||
| dma_generic_smoke | 9.000s | 1256.238us | 50 | 50 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| dma_csr_hw_reset | 1.000s | 22.543us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| dma_csr_rw | 2.000s | 20.149us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| dma_csr_bit_bash | 6.000s | 1138.197us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| dma_csr_aliasing | 8.000s | 1055.789us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| dma_csr_mem_rw_with_rand_reset | 2.000s | 61.433us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| dma_csr_rw | 2.000s | 20.149us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 8.000s | 1055.789us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_memory_region_lock | 5 | 5 | 100.00 | |||
| dma_memory_region_lock | 96.000s | 5550.094us | 5 | 5 | 100.00 | |
| dma_memory_tl_error | 3 | 3 | 100.00 | |||
| dma_memory_stress | 355.000s | 67726.782us | 3 | 3 | 100.00 | |
| dma_handshake_tl_error | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 394.000s | 228280.544us | 3 | 3 | 100.00 | |
| dma_handshake_stress | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 394.000s | 228280.544us | 3 | 3 | 100.00 | |
| dma_memory_stress | 3 | 3 | 100.00 | |||
| dma_memory_stress | 355.000s | 67726.782us | 3 | 3 | 100.00 | |
| dma_generic_stress | 5 | 5 | 100.00 | |||
| dma_generic_stress | 945.000s | 287812.552us | 5 | 5 | 100.00 | |
| dma_handshake_mem_buffer_overflow | 3 | 3 | 100.00 | |||
| dma_handshake_stress | 394.000s | 228280.544us | 3 | 3 | 100.00 | |
| dma_abort | 5 | 5 | 100.00 | |||
| dma_abort | 10.000s | 2613.597us | 5 | 5 | 100.00 | |
| dma_stress_all | 3 | 3 | 100.00 | |||
| dma_stress_all | 162.000s | 11040.337us | 3 | 3 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| dma_alert_test | 2.000s | 11.674us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| dma_intr_test | 2.000s | 24.622us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 5.000s | 749.828us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| dma_tl_errors | 5.000s | 749.828us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 1.000s | 22.543us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 20.149us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 8.000s | 1055.789us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 87.967us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| dma_csr_hw_reset | 1.000s | 22.543us | 1 | 1 | 100.00 | |
| dma_csr_rw | 2.000s | 20.149us | 5 | 5 | 100.00 | |
| dma_csr_aliasing | 8.000s | 1055.789us | 1 | 1 | 100.00 | |
| dma_same_csr_outstanding | 3.000s | 87.967us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| dma_illegal_addr_range | 13 | 13 | 100.00 | |||
| dma_mem_enabled | 24.000s | 1364.072us | 5 | 5 | 100.00 | |
| dma_generic_stress | 945.000s | 287812.552us | 5 | 5 | 100.00 | |
| dma_handshake_stress | 394.000s | 228280.544us | 3 | 3 | 100.00 | |
| dma_config_lock | 15 | 15 | 100.00 | |||
| dma_config_lock | 12.000s | 483.646us | 15 | 15 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| dma_tl_intg_err | 5.000s | 341.380us | 25 | 25 | 100.00 | |
| dma_sec_cm | 2.000s | 28.194us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 30 | 31 | 96.77 | |||
| dma_short_transfer | 216.000s | 17107.542us | 25 | 25 | 100.00 | |
| dma_longer_transfer | 18.000s | 1993.951us | 5 | 5 | 100.00 | |
| dma_stress_all_with_rand_reset | 20.000s | 2069.876us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ *ps: (cip_base_vseq.sv:1287) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 1 test run | |||
| dma_stress_all_with_rand_reset | 68403436439497269419984415536285107687740897125019817372760408826849157660517 | 132 |
UVM_INFO @ 2069876128ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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