Simulation Results: edn/edn0

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.30 %
  • code
  • 95.28 %
  • assert
  • 98.89 %
  • func
  • 58.74 %
  • block
  • 96.95 %
  • line
  • 98.68 %
  • branch
  • 93.23 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.35%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 3.000s 20.534us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 31.889us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 52.058us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.000s 150.812us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 3.000s 68.449us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 21.673us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 52.058us 5 5 100.00
edn_csr_aliasing 3.000s 68.449us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 8.000s 49.929us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 8.000s 49.929us 100 100 100.00
genbits 100 100 100.00
edn_genbits 8.000s 49.929us 100 100 100.00
interrupts 20 20 100.00
edn_intr 3.000s 32.564us 20 20 100.00
alerts 200 200 100.00
edn_alert 8.000s 32.145us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 76.611us 100 100 100.00
disable 90 100 90.00
edn_disable 2.000s 56.292us 50 50 100.00
edn_disable_auto_req_mode 14.000s 500.000us 40 50 80.00
stress_all 30 30 100.00
edn_stress_all 8.000s 494.145us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 36.094us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 3.000s 149.918us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.000s 124.400us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.000s 124.400us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.000s 31.889us 1 1 100.00
edn_csr_rw 2.000s 52.058us 5 5 100.00
edn_csr_aliasing 3.000s 68.449us 1 1 100.00
edn_same_csr_outstanding 3.000s 68.794us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.000s 31.889us 1 1 100.00
edn_csr_rw 2.000s 52.058us 5 5 100.00
edn_csr_aliasing 3.000s 68.449us 1 1 100.00
edn_same_csr_outstanding 3.000s 68.794us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 12.000s 681.183us 5 5 100.00
edn_tl_intg_err 4.000s 182.003us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 49.206us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 8.000s 32.145us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 12.000s 681.183us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 12.000s 681.183us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 12.000s 681.183us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 12.000s 681.183us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 8.000s 32.145us 200 200 100.00
edn_sec_cm 12.000s 681.183us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 8.000s 32.145us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.000s 182.003us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 30 80.00
edn_stress_all_with_rand_reset 91.000s 20806.963us 24 30 80.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:431) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 6 test runs
edn_disable_auto_req_mode 16476277869626439432820012144655727834509157641319937980391164717350846079178 103
UVM_INFO @ 18733911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 23369396542844737717065557747450439708558738128726153639828165464839490825142 103
UVM_INFO @ 40807512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 1469169745383004155460257725285132787349386826491694415770570665496575905607 103
UVM_INFO @ 29595374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 109009208892972611558661568123011454976733113108574288476959172094992310487721 103
UVM_INFO @ 22713664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 56560975051184155674339082427829110824275804487005438800351994787373167494216 103
UVM_INFO @ 24036869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 11504134853401197881469543588313418801627512863025100325416136800919440719152 103
UVM_INFO @ 21668486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
edn_stress_all_with_rand_reset 114807315340826077604531657617174957271956898248703582415109708044088121545692 175
UVM_INFO @ 1478308628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 46134429048007549032052795451441210748534315007441941641500805967946553346427 166
UVM_INFO @ 1629984755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 17833661773215452678411442884860022628941627673019923355007177307498582485208 250
UVM_INFO @ 1247622202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 16752632083454342671216050721927915635576288326608892879559047175993214882533 212
UVM_INFO @ 325037677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 112543563259708757215740815030272668012547222522432628090150927916254859798917 195
UVM_INFO @ 1135349721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 5999990012385161505493299584409952796790137394765320477759932372365199958193 204
UVM_INFO @ 1489130290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 4 test runs
edn_disable_auto_req_mode 100920937042302824287665436018337008539598944145845159633764877604176241071824 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 114440407641404970565837674122718015129782659210897759913983361052598570359870 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 96141754074083781278621699885578776107216071034854586756619105837245556995511 104
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 9178354464451667395111399118561565045268890713141066530372105076835912226566 103
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---