Simulation Results: edn/edn1

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.75 %
  • code
  • 96.37 %
  • assert
  • 98.44 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.92 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
98.85%
V2S
100.00%
V3
86.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.190s 126.117us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.250s 274.501us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.190s 14.047us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 1.850s 48.016us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.160s 32.043us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.500s 59.816us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.190s 14.047us 5 5 100.00
edn_csr_aliasing 1.160s 32.043us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 2.990s 338.432us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 2.990s 338.432us 100 100 100.00
genbits 100 100 100.00
edn_genbits 2.990s 338.432us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.390s 23.606us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.980s 511.588us 200 200 100.00
errs 100 100 100.00
edn_err 1.550s 95.631us 100 100 100.00
disable 93 100 93.00
edn_disable 1.200s 36.719us 50 50 100.00
edn_disable_auto_req_mode 7.890s 500.000us 43 50 86.00
stress_all 30 30 100.00
edn_stress_all 6.320s 340.882us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.110s 32.175us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.080s 27.343us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 3.370s 550.945us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 3.370s 550.945us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.250s 274.501us 1 1 100.00
edn_csr_rw 1.190s 14.047us 5 5 100.00
edn_csr_aliasing 1.160s 32.043us 1 1 100.00
edn_same_csr_outstanding 1.830s 478.756us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.250s 274.501us 1 1 100.00
edn_csr_rw 1.190s 14.047us 5 5 100.00
edn_csr_aliasing 1.160s 32.043us 1 1 100.00
edn_same_csr_outstanding 1.830s 478.756us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.120s 362.273us 5 5 100.00
edn_tl_intg_err 3.260s 147.024us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.190s 18.880us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.980s 511.588us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.120s 362.273us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.120s 362.273us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.120s 362.273us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.120s 362.273us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.980s 511.588us 200 200 100.00
edn_sec_cm 4.120s 362.273us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.980s 511.588us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.260s 147.024us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 26 30 86.67
edn_stress_all_with_rand_reset 95.580s 5406.332us 26 30 86.67

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 7 test runs
edn_disable_auto_req_mode 95621534262303938822883500969536565581570351478709476875975607872856807199737 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 6971189914436054118262079062612831473780674274409301275518448789004734451054 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 68244184238218895161859100494190348312169202661442190506268731741858257536134 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 55517216101381182145137717692695017149130696314891045183866412864215184055287 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 20033380838952356891921042194350030557407211919000781419163846572614895185324 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 71230169213180398520884239532378926192859868641581533940766630772420058186549 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 111863412108820731109029377717627418106097698796518344830607697282722004172154 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 20803725003998559311090621902412581930911737920110154586459297459666867774230 283
UVM_INFO @ 3219719678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 14756653974229567212541951615139421716775248470817354920694853423308020927168 223
UVM_INFO @ 1016608886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 11909863744274709341857455852991420830965914395218421629485563861671475547296 137
UVM_INFO @ 117821257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_stress_all_with_rand_reset 35891723702751370987607794678923134683338369186880484436431685894129857688987 111
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 48431748 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup