Simulation Results: hmac

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 96.11 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 96.96 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 18.000s 1558.806us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 39.102us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 89.587us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.000s 658.538us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 5.000s 209.575us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 624.000s 108719.762us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 89.587us 5 5 100.00
hmac_csr_aliasing 5.000s 209.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 95.000s 14430.953us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 115.000s 10193.167us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 349.000s 9902.959us 30 30 100.00
hmac_test_sha384_vectors 692.000s 192762.741us 75 75 100.00
hmac_test_sha512_vectors 667.000s 80590.619us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 6047.848us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 1147.635us 60 60 100.00
hmac_test_hmac512_vectors 29.000s 637.165us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 59.000s 4894.809us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 299.000s 143840.811us 10 10 100.00
error 10 10 100.00
hmac_error 137.000s 40556.705us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 150.000s 12315.402us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 18.000s 1558.806us 10 10 100.00
hmac_long_msg 95.000s 14430.953us 10 10 100.00
hmac_back_pressure 115.000s 10193.167us 25 25 100.00
hmac_datapath_stress 299.000s 143840.811us 10 10 100.00
hmac_burst_wr 59.000s 4894.809us 50 50 100.00
hmac_stress_all 1237.000s 432409.955us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 18.000s 1558.806us 10 10 100.00
hmac_long_msg 95.000s 14430.953us 10 10 100.00
hmac_back_pressure 115.000s 10193.167us 25 25 100.00
hmac_datapath_stress 299.000s 143840.811us 10 10 100.00
hmac_wipe_secret 150.000s 12315.402us 10 10 100.00
hmac_test_sha256_vectors 349.000s 9902.959us 30 30 100.00
hmac_test_sha384_vectors 692.000s 192762.741us 75 75 100.00
hmac_test_sha512_vectors 667.000s 80590.619us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 6047.848us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 1147.635us 60 60 100.00
hmac_test_hmac512_vectors 29.000s 637.165us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 18.000s 1558.806us 10 10 100.00
hmac_long_msg 95.000s 14430.953us 10 10 100.00
hmac_back_pressure 115.000s 10193.167us 25 25 100.00
hmac_datapath_stress 299.000s 143840.811us 10 10 100.00
hmac_burst_wr 59.000s 4894.809us 50 50 100.00
hmac_error 137.000s 40556.705us 10 10 100.00
hmac_wipe_secret 150.000s 12315.402us 10 10 100.00
hmac_test_sha256_vectors 349.000s 9902.959us 30 30 100.00
hmac_test_sha384_vectors 692.000s 192762.741us 75 75 100.00
hmac_test_sha512_vectors 667.000s 80590.619us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 6047.848us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 1147.635us 60 60 100.00
hmac_test_hmac512_vectors 29.000s 637.165us 75 75 100.00
hmac_stress_all 1237.000s 432409.955us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1237.000s 432409.955us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 82.606us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 29.117us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 7.000s 862.483us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 7.000s 862.483us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 39.102us 1 1 100.00
hmac_csr_rw 2.000s 89.587us 5 5 100.00
hmac_csr_aliasing 5.000s 209.575us 1 1 100.00
hmac_same_csr_outstanding 3.000s 107.781us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 39.102us 1 1 100.00
hmac_csr_rw 2.000s 89.587us 5 5 100.00
hmac_csr_aliasing 5.000s 209.575us 1 1 100.00
hmac_same_csr_outstanding 3.000s 107.781us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 118.616us 5 5 100.00
hmac_tl_intg_err 17.000s 1099.797us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 17.000s 1099.797us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 18.000s 1558.806us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 10.000s 327.140us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 234.000s 56888.527us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.000s 11.263us 1 1 100.00