Simulation Results: lc_ctrl/volatile_unlock_disabled

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.98 %
  • code
  • 93.16 %
  • assert
  • 95.97 %
  • func
  • 89.81 %
  • block
  • 96.66 %
  • line
  • 97.35 %
  • branch
  • 91.49 %
  • toggle
  • 88.57 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.53%
V2S
99.33%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 7.000s 238.429us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 22.000s 21.537us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 19.000s 104.329us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 24.000s 1585.544us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 22.000s 99.216us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 20.000s 21.022us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 19.000s 104.329us 5 5 100.00
lc_ctrl_csr_aliasing 22.000s 99.216us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 978.355us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 12.000s 357.448us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 22.000s 111.559us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 305.197us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 23.000s 373.529us 20 20 100.00
security_escalation 139 140 99.29
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_ctrl_prog_failure 4.000s 305.197us 20 20 100.00
lc_ctrl_errors 23.000s 373.529us 20 20 100.00
lc_ctrl_security_escalation 12.000s 474.832us 20 20 100.00
lc_ctrl_jtag_state_failure 47.000s 11736.622us 20 20 100.00
lc_ctrl_jtag_prog_failure 21.000s 817.470us 19 20 95.00
lc_ctrl_jtag_errors 55.000s 3155.194us 20 20 100.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 9.000s 407.732us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 1227.671us 19 20 95.00
lc_ctrl_jtag_prog_failure 21.000s 817.470us 19 20 95.00
lc_ctrl_jtag_errors 55.000s 3155.194us 20 20 100.00
lc_ctrl_jtag_access 23.000s 2695.722us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.000s 7259.496us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 15.000s 226.244us 10 10 100.00
lc_ctrl_jtag_csr_rw 7.000s 96.328us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 36.000s 7008.026us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 28.000s 3328.857us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 32.692us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 10.000s 171.140us 10 10 100.00
lc_ctrl_jtag_alert_test 17.000s 552.401us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 21.000s 3296.775us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.882us 10 10 100.00
stress_all 10 10 100.00
lc_ctrl_stress_all 149.000s 7830.055us 10 10 100.00
alert_test 10 10 100.00
lc_ctrl_alert_test 22.000s 23.454us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 6.000s 628.123us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 6.000s 628.123us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 22.000s 21.537us 1 1 100.00
lc_ctrl_csr_rw 19.000s 104.329us 5 5 100.00
lc_ctrl_csr_aliasing 22.000s 99.216us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 165.590us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 22.000s 21.537us 1 1 100.00
lc_ctrl_csr_rw 19.000s 104.329us 5 5 100.00
lc_ctrl_csr_aliasing 22.000s 99.216us 1 1 100.00
lc_ctrl_same_csr_outstanding 3.000s 165.590us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 6.000s 250.520us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 81.897us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 81.897us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 12.000s 357.448us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_ctrl_sec_cm 6.000s 250.520us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_ctrl_sec_cm 6.000s 250.520us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_ctrl_sec_cm 6.000s 250.520us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_ctrl_sec_cm 6.000s 250.520us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_ctrl_sec_cm 6.000s 250.520us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_ctrl_sec_cm 6.000s 250.520us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_ctrl_sec_cm 6.000s 250.520us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 12.000s 426.781us 20 20 100.00
lc_ctrl_sec_cm 6.000s 250.520us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 12.000s 474.832us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 4.000s 978.355us 20 20 100.00
lc_ctrl_jtag_state_post_trans 22.000s 1227.671us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.000s 643.352us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 14.000s 643.352us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 12.000s 2890.757us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.000s 430.921us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 11.000s 430.921us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 10 50.00
lc_ctrl_stress_all_with_rand_reset 45.000s 10999.849us 5 10 50.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 93341963135985991878996220928386449707429771477637960530496261490891695868030 1477
UVM_INFO @ 10841026800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1601710200971323449299015022033942234250933766272006640544165594930201142338 172
UVM_INFO @ 4094081691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 99186693282278933049054081495532840891529897349680450870838666112530519162940 2918
UVM_INFO @ 7301597900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 64061500292473328785994009057049573036325105902187560039022296785109017296583 943
UVM_INFO @ 14225905489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 31062765947502197702291462693068686197838714147700110305045715917951895653066 462
UVM_INFO @ 4112830278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 1 test run
lc_ctrl_jtag_prog_failure 26625410924161105928198961969016084257931247778192378152072748893481926470285 177
UVM_INFO @ 221503575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 1 test run
lc_ctrl_jtag_state_post_trans 35762575465832370651377718866896338407378481928391769535570195270735282814715 178
UVM_INFO @ 108243490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---