Simulation Results: lc_ctrl/volatile_unlock_enabled

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.31 %
  • code
  • 94.15 %
  • assert
  • 95.97 %
  • func
  • 89.81 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 88.60 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
99.06%
V2S
99.33%
V3
30.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.000s 88.329us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 2.000s 31.158us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 56.226us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 135.668us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 16.509us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 67.116us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 56.226us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 16.509us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 5.000s 261.055us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 10.000s 545.565us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 13.766us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 102.602us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 13.000s 1494.875us 20 20 100.00
security_escalation 138 140 98.57
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_ctrl_prog_failure 4.000s 102.602us 20 20 100.00
lc_ctrl_errors 13.000s 1494.875us 20 20 100.00
lc_ctrl_security_escalation 9.000s 516.889us 20 20 100.00
lc_ctrl_jtag_state_failure 69.000s 4267.960us 18 20 90.00
lc_ctrl_jtag_prog_failure 13.000s 2375.394us 20 20 100.00
lc_ctrl_jtag_errors 71.000s 8708.126us 20 20 100.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 11.000s 1243.848us 20 20 100.00
lc_ctrl_jtag_state_post_trans 20.000s 12689.007us 19 20 95.00
lc_ctrl_jtag_prog_failure 13.000s 2375.394us 20 20 100.00
lc_ctrl_jtag_errors 71.000s 8708.126us 20 20 100.00
lc_ctrl_jtag_access 28.000s 6310.029us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.000s 6987.932us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 270.390us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 399.974us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 21.000s 1804.179us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 19.000s 1321.951us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 3.000s 595.953us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 6.000s 1231.944us 10 10 100.00
lc_ctrl_jtag_alert_test 3.000s 143.209us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 25.000s 1514.112us 10 10 100.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 15.261us 10 10 100.00
stress_all 9 10 90.00
lc_ctrl_stress_all 228.000s 44704.499us 9 10 90.00
alert_test 10 10 100.00
lc_ctrl_alert_test 3.000s 29.932us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 289.104us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 5.000s 289.104us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 31.158us 1 1 100.00
lc_ctrl_csr_rw 2.000s 56.226us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 16.509us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 198.070us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 2.000s 31.158us 1 1 100.00
lc_ctrl_csr_rw 2.000s 56.226us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 16.509us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 198.070us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 5.000s 292.978us 5 5 100.00
lc_ctrl_tl_intg_err 4.000s 534.224us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 4.000s 534.224us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 10.000s 545.565us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_ctrl_sec_cm 5.000s 292.978us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_ctrl_sec_cm 5.000s 292.978us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_ctrl_sec_cm 5.000s 292.978us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_ctrl_sec_cm 5.000s 292.978us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_ctrl_sec_cm 5.000s 292.978us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_ctrl_sec_cm 5.000s 292.978us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_ctrl_sec_cm 5.000s 292.978us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 8.000s 386.838us 20 20 100.00
lc_ctrl_sec_cm 5.000s 292.978us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 9.000s 516.889us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 39 40 97.50
lc_ctrl_state_post_trans 5.000s 261.055us 20 20 100.00
lc_ctrl_jtag_state_post_trans 20.000s 12689.007us 19 20 95.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.000s 807.550us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.000s 807.550us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 10.000s 1527.349us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.000s 2459.588us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 12.000s 2459.588us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
lc_ctrl_stress_all_with_rand_reset 38.000s 12771.854us 3 10 30.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
lc_ctrl_stress_all_with_rand_reset 60600663402665939805021658649124059469820281298445471396428203669237861083029 2723
UVM_INFO @ 1943938184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 112145146025935847297409007269247867727543967876428832918145783990892036008769 161
UVM_INFO @ 1143823766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30411983020889014659046848046006467021722896579203491884405483778669343395172 2051
UVM_INFO @ 12771854067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80135125472194425765050854141415687069461941035225372108315691461179702649260 4211
UVM_INFO @ 5674068194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 45403431503150661911187510879367974170944835820588549716257569218709300183708 1468
UVM_INFO @ 2906407628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 114451849618300781205177047936806214372114874270018132839162027559322948205536 3303
UVM_INFO @ 1842887285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 3 test runs
lc_ctrl_jtag_state_failure 60077809078228608550862263084787475947676927442543645489022030927365188467941 178
UVM_INFO @ 275215132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 75913149798898747879937371637663575281571395462957864419384466346418976689827 178
UVM_INFO @ 285052431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 81156127475057030124882135964617347832211481146058230704839384387922795150779 180
UVM_INFO @ 68047568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1200) [lc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
lc_ctrl_stress_all_with_rand_reset 17691131536284299510335693457773531308897423697080329368996631261804868363530 1975
UVM_INFO @ 8645862091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* 1 test run
lc_ctrl_stress_all 4498856106802683872695528778764967810002652525457784320336296992222632321578 6955
UVM_INFO @ 44704499197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---