Simulation Results: otbn

 
17/07/2026 15:00:31 DVSim: v1.49.0 sha: df7ce05 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.92 %
  • code
  • 87.13 %
  • assert
  • 97.64 %
  • func
  • 100.00 %
  • block
  • 99.38 %
  • line
  • 99.57 %
  • branch
  • 95.52 %
  • toggle
  • 85.81 %
  • FSM
  • 67.61 %
Validation stages
V1
100.00%
V2
96.93%
V2S
97.87%
V3
30.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 17.000s 215.960us 1 1 100.00
single_binary 100 100 100.00
otbn_single 92.000s 612.704us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 7.000s 43.697us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 7.000s 102.760us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 11.000s 189.641us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 7.000s 25.389us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 9.000s 148.889us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 7.000s 102.760us 5 5 100.00
otbn_csr_aliasing 7.000s 25.389us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 157.000s 28059.414us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 28.000s 4283.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 111.000s 538.221us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 64.000s 384.163us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 352.000s 14555.888us 10 10 100.00
stress_all 9 10 90.00
otbn_stress_all 181.000s 2654.959us 9 10 90.00
lc_escalation 58 60 96.67
otbn_escalate 47.000s 556.895us 58 60 96.67
zero_state_err_urnd 3 5 60.00
otbn_zero_state_err_urnd 7.000s 25.688us 3 5 60.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 27.000s 67.324us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 9.000s 22.631us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 7.000s 50.363us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 8.000s 537.725us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 8.000s 537.725us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 7.000s 43.697us 1 1 100.00
otbn_csr_rw 7.000s 102.760us 5 5 100.00
otbn_csr_aliasing 7.000s 25.389us 1 1 100.00
otbn_same_csr_outstanding 7.000s 25.762us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 7.000s 43.697us 1 1 100.00
otbn_csr_rw 7.000s 102.760us 5 5 100.00
otbn_csr_aliasing 7.000s 25.389us 1 1 100.00
otbn_same_csr_outstanding 7.000s 25.762us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 16.000s 52.148us 10 10 100.00
otbn_dmem_err 19.000s 38.635us 15 15 100.00
internal_integrity 16 17 94.12
otbn_alu_bignum_mod_err 11.000s 25.359us 5 5 100.00
otbn_controller_ispr_rdata_err 17.000s 99.839us 5 5 100.00
otbn_mac_bignum_acc_err 20.000s 44.511us 4 5 80.00
otbn_urnd_err 5.000s 25.976us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 15.000s 54.180us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 7.000s 13.833us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 9.000s 27.246us 10 10 100.00
tl_intg_err 30 30 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
otbn_tl_intg_err 64.000s 357.202us 25 25 100.00
passthru_mem_tl_intg_err 5 5 100.00
otbn_passthru_mem_tl_intg_err 66.000s 232.996us 5 5 100.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 17.000s 215.960us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 19.000s 38.635us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 16.000s 52.148us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 64.000s 357.202us 25 25 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 47.000s 556.895us 58 60 96.67
sec_cm_controller_fsm_local_esc 38 40 95.00
otbn_imem_err 16.000s 52.148us 10 10 100.00
otbn_dmem_err 19.000s 38.635us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 25.688us 3 5 60.00
otbn_illegal_mem_acc 15.000s 54.180us 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 92.000s 612.704us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 16.000s 52.148us 10 10 100.00
otbn_dmem_err 19.000s 38.635us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 25.688us 3 5 60.00
otbn_illegal_mem_acc 15.000s 54.180us 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 47.000s 556.895us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 16.000s 52.148us 10 10 100.00
otbn_dmem_err 19.000s 38.635us 15 15 100.00
otbn_zero_state_err_urnd 7.000s 25.688us 3 5 60.00
otbn_illegal_mem_acc 15.000s 54.180us 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 92.000s 612.704us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 19.000s 58.982us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 9.000s 25.554us 5 5 100.00
sec_cm_rnd_bus_consistency 4 5 80.00
otbn_rnd_sec_cm 77.000s 155.634us 4 5 80.00
sec_cm_rnd_rng_digest 4 5 80.00
otbn_rnd_sec_cm 77.000s 155.634us 4 5 80.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 12.000s 83.922us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 20.000s 43.475us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 15.000s 43.120us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 15.000s 43.120us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 15.000s 97.260us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 92.000s 612.704us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 92.000s 612.704us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 92.000s 612.704us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 352.000s 14555.888us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 92.000s 612.704us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 92.000s 612.704us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 15.000s 48.398us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 92.000s 612.704us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 226.000s 875.705us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 10 30.00
otbn_stress_all_with_rand_reset 488.000s 1767.583us 3 10 30.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 9.000s 19.259us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
otbn_stress_all_with_rand_reset 25676479441253918913207527836987833010586049596056770716429033525271735449487 180
UVM_INFO @ 2000538187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 110580373911571569528471555086409301108636947733036912712090979884695153019358 466
UVM_INFO @ 1710803976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 29772956027065553132260514673148587987817275694742598762877759421549376110358 400
UVM_INFO @ 2244476427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 40728722370107949960603681592573575399349076524897061552935171000430357512775 174
UVM_INFO @ 1150635647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 52104094133476907326899939016598263533782756630541927111174555627049635690991 425
UVM_INFO @ 1767583311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 3 test runs
otbn_zero_state_err_urnd 26363869700273632914352405255864571733314005816557502648673868439815971595097 112
UVM_ERROR @ 29869948 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 29869948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_zero_state_err_urnd 41623824004126634381335807744923850961899662847392461953471334602321501667537 111
UVM_ERROR @ 34969051 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 34969051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 95253774881147671880803783839704410211184463428662030031100233703052078429409 115
UVM_ERROR @ 43867709 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 43867709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_mac_bignum_acc_err 39126409714766316861146171566537475618306870944295172688895111309617897358357 120
UVM_INFO @ 35480370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 47895912687677996791528326970386000047549609843369896606958693666427682330386 111
UVM_INFO @ 142396506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 2 test runs
otbn_stress_all 36233719184009390750662855899574532234148219572270478688114650657573574360384 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
otbn_stress_all_with_rand_reset 103650557664528061677867385519191395866627480141452994009832539231405216218934 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_rnd_sec_cm 32275323663416504008152771555501850753691498453720446681072262288218918227515 123
UVM_INFO @ 225022112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1049) virtual_sequencer [otbn_rf_bignum_intg_err_vseq] Expected alert (fatal) did not fire in * cycles. 1 test run
otbn_rf_bignum_intg_err 109903639818201730851098662186465113692210462046742872990591422060826446898243 116
UVM_INFO @ 47145841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 111629938062022552448181580690923323470504959997062768970183758073695717142253 166
UVM_INFO @ 2754868112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---